Three-dimensional capacitors with double metal electrodes

Patent metadata

Field	Value
Publication number	US-12176147-B2
Application number	US-202117357385-A
Country	US
Kind code	B2
Filing date	Jun 24, 2021
Priority date	Jun 24, 2021
Publication date	Dec 24, 2024
Grant date	Dec 24, 2024

Abstract

Disclosed herein are IC structures with three-dimensional capacitors with double metal electrodes provided in a support structure (e.g., a substrate, a die, a wafer, or a chip). An example three-dimensional capacitor includes first and second capacitor electrodes and a capacitor insulator between them. Each capacitor electrode includes a planar portion extending across the support structure and one or more via portions extending into one or more via openings in the support structure. The capacitor insulator also includes a planar portion and a via portion extending into the via opening(s). The planar portion of the capacitor electrodes are thicker than the via portions. Each capacitor electrode may be deposited using two deposition processes, such as a conformal deposition process for depositing the via portion of the electrode, and a sputter process for depositing the planar portion of the electrode.

First claim

The invention claimed is:

1. An integrated circuit (IC) device, comprising:
a support structure having a first face, a second face opposite the first face, and an opening extending from the second face towards, but not reaching, the first face; and
a capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator between the first capacitor electrode and the second capacitor electrode, wherein:
a first portion of the first capacitor electrode extends along an inner wall of the opening, and a second portion of the first capacitor electrode extends along at least a portion of the second face of the support structure;
a first portion of the capacitor insulator is nested within the first portion of the first capacitor electrode, and a second portion of the capacitor insulator is layered over the second portion of the first capacitor electrode; and
a first portion of the second capacitor electrode is nested within the first portion of the capacitor insulator, and a second portion of the second capacitor electrode is layered over the second portion of the capacitor insulator.

2. The IC device according to claim 1 , further comprising a first electrode contact electrically coupled to the first capacitor electrode, the first electrode contact in contact with the second portion of the first capacitor electrode, and a second electrode contact electrically coupled to the second capacitor electrode, the second electrode contact in contact with the second portion of the first capacitor electrode.

3. The IC device according to claim 1 , wherein the first capacitor electrode comprises a first conductive layer and a second conductive layer, the first conductive layer thinner than the second conductive layer.

4. The IC device according to claim 3 , the first conductive layer comprising:
the first portion of the first capacitor electrode; and
a first layer of the second portion of the first capacitor electrode.

5. The IC device according to claim 4 , the second conductive layer comprising a second layer of the second portion of the first capacitor electrode.

6. The IC device according to claim 3 , wherein the second capacitor electrode comprises a third conductive layer and a fourth conductive layer, the third conductive layer thinner than the fourth conductive layer.

7. The IC device according to claim 6 , the third conductive layer comprising:
the first portion of the second capacitor electrode; and
a second layer of the second portion of the second capacitor electrode.

8. The IC device according to claim 1 , wherein the first portion of the first capacitor electrode has a thickness between 1 nm and 5 nm, the second portion of the first capacitor electrode has a thickness between 10 nm and 100 nm, the first portion of the second capacitor electrode has a thickness between 1 nm and 5 nm, and the second portion of the second capacitor electrode has a thickness between 10 nm and 100 nm.

9. The IC device according to claim 1 , further comprising a transistor coupled to the capacitor, where the transistor and the capacitor are included in a memory cell.

10. The IC device according to claim 1 , the capacitor further comprising a third capacitor electrode and a second capacitor insulator between the second capacitor electrode and the third capacitor electrode.

11. The IC device according to claim 10 , wherein a first portion of the second capacitor insulator is nested within the first portion of the second capacitor electrode, and a first portion of the third capacitor electrode is nested within the first portion of the second capacitor electrode.

12. An integrated circuit (IC) device, comprising:
a support structure having a first face and a second face opposite the first face, the support structure having an array of openings, each opening extending from the second face towards, but not reaching, the first face of the support structure, and each opening having an inner wall; and
a capacitor comprising:
a first conductive layer comprising a first array of conductive via portions extending along the inner walls of the array of openings, and a planar portion extending along the second face of the support structure, the planar portion of the first conductive layer electrically connecting the first array of conductive via portions;
an insulator layer comprising an array of insulating via portions nested within the first array of conductive via portions, and a planar portion extending parallel to the second face of the support structure; and
a second conductive layer comprising a second array of conductive via portions nested within the array of insulating via portions, and a planar portion extending parallel to the second face of the support structure, the planar portion of the second conductive layer electrically connecting the second array of conductive via portions.

13. The IC device of claim 12 , wherein neighboring openings in the array have a pitch between 50 nm and 500 nm.

14. The IC device of claim 12 , wherein an opening in the array has a diameter between 50 nm and 500 nm.

15. The IC device of claim 12 , the capacitor further comprising:
a second insulator layer comprising a second array of insulating via portions nested within the second array of conductive via portions, and a planar portion extending parallel to the second face of the support structure; and
a third conductive layer comprising a third array of conductive via portions nested within the second array of insulating via portions, and a planar portion extending parallel to the second face of the support structure.

16. The IC device according to claim 15 , wherein the first conductive layer and the third conductive layer are electrically coupled to a first electrode contact, and the second conductive layer is electrically coupled to a second electrode contact.

17. The IC device according to claim 15 , wherein the first conductive layer is electrically coupled to a first electrode contact, the second conductive layer is electrically coupled to a second electrode contact, and the third conductive layer is electrically coupled to a third electrode contact.

18. The IC device according to claim 12 , wherein the capacitor is a decoupling capacitor.

19. A method for fabricating an integrated circuit (IC) structure, the method comprising:
forming, in a support structure, an array of via openings;
forming, using a first deposition method, a first capacitor electrode layer over the support structure and in the array of via openings;
forming, using a second deposition method, a second capacitor electrode layer over the first capacitor electrode layer;
forming an insulator layer over the second capacitor electrode layer and in the array of via openings;
forming, using the first deposition method, a third capacitor electrode layer over the insulator layer and in the array of via openings;
forming, using the second deposition method, a fourth capacitor electrode layer over the third capacitor electrode layer.

20. The method according to claim 19 , further comprising:
forming a first electrode contact for the first capacitor electrode; and
forming a second capacitor electrode for the second capacitor electrode.

Assignees

• Intel Corp

Inventors

• Waldemer James D
• Giraud-Carrier Matthieu
• Sell Bernhard
• Lajoie Travis W
• Gomes Wilfred
• Sharma Abhishek A

Classifications

• H01G4/40

  Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations · CPC title

• H01G4/30

  Stacked capacitors (H01G4/33 takes precedence) · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D84/212

  of only capacitors · CPC title