Neuromorphic architecture

Patent metadata

Field	Value
Publication number	US-12175358-B2
Application number	US-202117248373-A
Country	US
Kind code	B2
Filing date	Jan 22, 2021
Priority date	Jan 24, 2020
Publication date	Dec 24, 2024
Grant date	Dec 24, 2024

Abstract

The present disclosure relates to a routing circuit for routing signals between neuron circuits of an artificial neural network, the routing circuit comprising: a first memory cell ( 302 ) having an input coupled to a first input line ( 304 ) of the routing circuit and an output coupled to a first column line ( 308 ); a second memory cell ( 302 ) having an input coupled to a second input line ( 304 ) of the routing circuit and an output coupled to the first column line ( 308 ); and a first comparator circuit ( 310 ) configured to compare a signal (IREAD 1 ) on the first column line ( 308 ) with a reference level, and to selectively assert a signal (VOUT 1 ) on a first output line ( 312 ) of the routing circuit based on the comparison.

First claim

What is claimed is:

1. An artificial neural network comprising:
a plurality of routing circuits; and
a plurality of neuron circuits not forming part of the plurality of routing circuits, each neuron circuit having at least one input line and at least one output line;
each routing circuit of the plurality of routing circuits coupling one or more output lines of one or more first neuron circuits among the plurality of neuron circuits to one or more input lines of one or more second neuron circuits among the plurality of neuron circuits, wherein each routing circuit comprises:
a first memory cell having an input coupled to a first input line of the routing circuit and an output coupled to a first column line;
a second memory cell having an input coupled to a second input line of the routing circuit and an output coupled to the first column line; and
a first comparator circuit configured to compare a signal on the first column line with a reference level, and to selectively assert a signal on a first output line of the routing circuit based on the comparison.

2. The artificial neural network of claim 1 , wherein the first comparator circuit has an input connected to the first column line, and the first comparator circuit does not comprise a neuron soma.

3. The artificial neural network of claim 1 , wherein the first and second memory cells store routing data indicating a routing to be applied between the one or more output lines of the one or more neuron circuits and the one or more input lines of the one or more neuron circuits.

4. The artificial neural network of claim 1 , wherein each routing circuit further comprises:
a third memory cell having an input coupled to the first input line of the routing circuit and an output coupled to a second column line;
a fourth memory cell having an input coupled to the second input line of the routing circuit and an output coupled to the second column line; and
a second comparator circuit configured to compare a signal on the second column line with a reference level, and to selectively assert a signal on a second output line of the routing circuit based on the comparison.

5. The artificial neural network of claim 1 , wherein:
the first memory cell is configured to store a first activation bit, wherein the first memory cell is configured to assert a signal on the first column line when the first activation bit and a signal on the first input line of the routing circuit are asserted; and
the second memory cell is configured to store a second activation bit, wherein the second memory cell is configured to assert a signal on the first column line when the second activation bit and a signal on the second input line of the routing circuit are asserted.

6. The artificial neural network of claim 5 , wherein the first and second memory cells are configured to assert current signals on the first column line.

7. The artificial neural network of claim 1 , wherein first and second memory cells comprise non-volatile storage elements, such as resistive memory elements.

8. The artificial neural network of claim 1 , wherein each neuron circuit comprises:
a first memory cell having an input coupled to a first input line of the neuron circuit and an output coupled to a first column line of the neuron circuit;
a second memory cell having an input coupled to a second input line of the routing circuit and an output coupled to the first column line of the neuron circuit; and
a first computation circuit comprising a first neuron soma.

9. The artificial neural network of claim 8 , wherein the first and second memory cells of each neuron circuit each store a synaptic weight.

10. The artificial neural network of claim 8 , further comprising:
a third memory cell having an input coupled to the first input line of the neuron circuit and an output coupled to a second column line of the neuron circuit;
a fourth memory cell having an input coupled to the second input line of the neuron circuit and an output coupled to the second column line; and
a second computation circuit comprising a second neuron soma.

11. The artificial neural network of claim 1 , comprising an array of tiles, each tile of the array being either one of the routing circuits or one of the neuron circuits, wherein interconnections are formed between neighboring tiles in the array.

12. The artificial neural network of claim 11 , wherein the array is configured such that each neuron circuit is coupled to one or more other neuron circuits of the array via one of the routing circuits, or via the series connection of a plurality of the routing circuits.

13. The artificial neural network of claim 12 , wherein the array is arranged such that each neuron circuit has at least four neighboring routing circuits.

14. The artificial neural network of claim 1 , wherein the plurality of neuron circuits and the plurality of routing circuits are formed in a plurality of layers of a 3-dimensional circuit structure.

15. A method of routing signals between neuron circuits of an artificial neural network, the artificial neural network comprising: a plurality of routing circuits, a plurality of neuron circuits not forming part of the plurality of routing circuits, each neuron circuit having at least one input line and at least one output line; each routing circuit of the plurality of routing circuits coupling one or more output lines of one or more first neuron circuits among the plurality of neuron circuits to one or more input lines of one or more second neuron circuits among the plurality of neuron circuits, the method comprising:
programming a first memory cell of a first of the routing circuits, the first memory cell having an input coupled to a first input line of the first routing circuit and an output coupled to a first column line;
programming a second memory cell of the first routing circuit, the second memory cell having an input coupled to a second input line of the routing circuit and an output coupled to the first column line;
comparing, by a first comparator circuit, a signal on the first column line with a reference level; and
selectively asserting a signal on a first output line of the routing circuit based on the comparison.

Assignees

• Commissariat A Ienergie Atomique Et Aux Energies Alternatives
• Univ Zuerich
• Commissariat Energie Atomique

Inventors

• Dalgaty Thomas
• Indiveri Giacomo
• Payvand Melika
• Vianello Elisas

Classifications

• G06N3/0442

  characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU] · CPC title

• G06N3/0495

  Quantised networks; Sparse networks; Compressed networks · CPC title

• H10B63/80

  Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays · CPC title

• G06N3/04

  Architecture, e.g. interconnection topology · CPC title

• G06N3/065

  Analogue means · CPC title