Arithmetic apparatus, operating method thereof, and neural network processor

Patent metadata

Field	Value
Publication number	US-12175208-B2
Application number	US-202016989391-A
Country	US
Kind code	B2
Filing date	Aug 10, 2020
Priority date	Dec 6, 2019
Publication date	Dec 24, 2024
Grant date	Dec 24, 2024

Abstract

An arithmetic apparatus includes a first operand holding circuit configured to output a first operand according to a clock signal, generate an indicator signal based on bit values of high-order bit data including a most significant bit of the first operand, and gate the clock signal based on the indicator signal, the clock signal being applied to a flip-flop latching the high-order bit data of the first operand; a second operand holding circuit configured to output a second operand according to the clock signal; and an arithmetic circuit configured to perform data gating on the high-order bit data of the first operand based on the indicator signal and output an operation result by performing an operation using a modified first operand resulting from the data gating and the second operand.

First claim

What is claimed is:

1. An arithmetic apparatus for use in a neural network to perform real time analysis of input data under a power consumption constraint, the arithmetic apparatus comprising:
a first operand holding circuit configured to:
generate an indicator signal based on bit values of high-order bit data of a first operand, wherein the first operand is included in an input feature map of the neural network, and wherein the first operand is input to the first operand holding circuit, the high-order bit data of the first operand including a most significant bit of the first operand,
gate a clock signal, wherein the clock signal is input to the first operand holding circuit based on the indicator signal, to generate a first gated clock signal,
generate latched high-order bit data of the first operand based on the first gated clock signal being applied to a flip-flop latching the high-order bit data of the first operand, and
output bit data of the first operand, the bit data of the first operand comprising the latched high-order bit data of the first operand and low-order bit data of the first operand;
a second operand holding circuit configured to maintain and output a second operand input to the second operand holding circuit based on the clock signal, regardless of bit values of high-order bit data of the second operand including the most significant bit of the second operand, wherein the second operand is included in a weight matrix of the neural network; and
an arithmetic circuit comprises:
a first clock gating circuit configured to generate a second gated clock signal by gating the clock signal based on the logic level of the indicator signal; and
a high-order bit flip-flop configured to receive the latched high-order bit data of the first operand from the first operand holding circuit, receive the second gated clock signal from the first clock gating circuit, and latch the latched high-order bit data of the first operand based on the second gated clock signal,
wherein the arithmetic circuit is further configured to:
perform data gating on the latched high-order bit data of the first operand based on the indicator signal, to generate data-gated high-order bit data of the first operand, and
output an operation result by performing an operation using a modified first operand comprising the data-gated high-order bit data of the first operand and the low-order bit data of the first operand and the second operand, wherein the operation result corresponds to a convolution operation of the neural network based on the input feature map and the weight matrix.

2. The arithmetic apparatus of claim 1 , wherein the first operand holding circuit comprises a zero determination circuit configured to generate the indicator signal having a first logic level based on all the bit values of the high-order bit data of the first operand being “0” and a second logic level based on at least one of the bit values of the high-order bit data of the first operand not being “0”.

3. The arithmetic apparatus of claim 1 , wherein the first operand holding circuit comprises:
a high-order bit flip-flop configured to latch the high-order bit data of the first operand based on the first gated clock signal, to generate the latched high-order bit data of the first operand; and
a low-order bit flip-flop configured to latch the low-order bit data of the first operand based on the clock signal.

4. The arithmetic apparatus of claim 3 , wherein the first operand holding circuit further comprises a second clock gating circuit configured to generate the first gated clock signal by gating the clock signal according to a logic level of the indicator signal and provide the first gated clock signal to the high-order bit flip-flop.

5. The arithmetic apparatus of claim 1 , wherein the arithmetic circuit comprises:
a data gating circuit configured to generate the data-gated high-order bit data of the first operand by selectively passing the latched high-order bit data of the first operand based on a logic level of the indicator signal; and
a calculation circuit configured to generate the operation result by performing the operation using the data-gated high-order bit data of the first operand, the low-order bit data of the first operand, and the second operand.

6. The arithmetic apparatus of claim 5 , wherein the arithmetic circuit further comprises:
a low-order bit flip-flop configured to latch the low-order bit data of the first operand based on the clock signal.

7. The arithmetic apparatus of claim 5 , wherein the arithmetic circuit further comprises:
a multiplication circuit configured to generate a multiplication result by performing multiplication using the modified first operand and the second operand, and
an accumulation circuit configured to output the operation result by accumulating and summing at least one value of the multiplication result.

8. The arithmetic apparatus of claim 5 , wherein the multiplication circuit comprises:
a first multiplier configured to generate a first multiplication result by multiplying the low-order bit data of the first operand by the second operand;
a second multiplier configured to generate a second multiplication result by multiplying the data-gated high-order bit data of the first operand by the second operand;
a shifter configured to generate a shifted second multiplication result by shifting the second multiplication result by a number of bits in the low-order bit data of the first operand; and
an adder configured to add the shifted second multiplication result to the first multiplication result.

9. An arithmetic apparatus for use in a neural network to perform real time analysis of input data under a power consumption constraint, the arithmetic apparatus comprising:
a first operand holding circuit configured to generate a first gated clock signal by gating a clock signal based on the logic level of an indication signal generated based on bit values of high-order bit data of a first operand, latch the high-order bit data of the first operand based on the first gated clock signal, output a modified first operand based on the first gated clock signal and the clock signal, the modified first operand comprising a first latched high-order bit data of the first operand, wherein the first operand is included in an input feature map of the neural network, and wherein the first operand is input to the first operand holding circuit, and low-order bit data of the first operand;
a second operand holding circuit configured to maintain and output a second operand input to the second operand holding circuit based on the clock signal, regardless of bit values of high-order bit data of the second operand including the most significant bit of the second operand, wherein the second operand is included in a weight matrix of the neural network; and
an arithmetic circuit configured to output an operation result by performing an operation using the modified first operand and the second operand, wherein the operation result corresponds to a convolution operation of the neural network based on the input feature map and the weight matrix, and wherein the arithmetic circuit comprises:
a first clock gating circuit configured to generate a second gated clock signal by selectively passing the clock signal based on values of the high-order bit data of the first operand;
a first flip-flop configured to latch the first latched high-order bit data of the first operand based on the second gated clock signal to output second latched high-order bit data of the first operand; and
a second flip-flop configured to latch the low-order bit data of the first operand based on the clock signal.

10. The arithmetic apparatus of cl

Assignees

• Samsung Electronics Co Ltd

Inventors

• Song Jinook
• Kim Daekyeung
• Park Junseok
• Song Joonho
• Lee Sehwan
• Jang Junwoo
• Cho Yunkyo

Classifications

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06F2207/382

  Reconfigurable for different fixed word lengths · CPC title

• G06N3/063 Primary

  using electronic means · CPC title

• G06N3/04

  Architecture, e.g. interconnection topology · CPC title

• G06N3/045

  Combinations of networks · CPC title