Scalable analog PIM module, method of controlling analog PIM, signal processing circuit, and sensor device

Patent metadata

Field	Value
Publication number	US-12174595-B2
Application number	US-202217826168-A
Country	US
Kind code	B2
Filing date	May 27, 2022
Priority date	Dec 14, 2021
Publication date	Dec 24, 2024
Grant date	Dec 24, 2024

Abstract

Provided are a scalable analog passive intermodulation (PIM) module, a method of controlling analog PIM, a signal processing circuit, and a sensor device. The scalable analog PIM module includes a first plural number of digital-to-analog converters (DACs), a first plural number of static random access memory (SRAM) calculators connected to the first plural number of DACs, at least one analog-to-digital converter (ADC) connected to the first plural number of SRAM calculators and configured to convert an analog convolution result signal into digital convolution data, and an analog PIM controller configured to output an enable control signal for enabling a second number, which is equal to or less than first plural number, of SRAM calculators among the first plural number of SRAM calculators to the first plural number of SRAM calculators on the basis of the convolution data output from the ADC.

First claim

What is claimed is:

1. A scalable analog passive intermodulation (PIM) module comprising:
a first plural number of digital-to-analog converters (DACs);
a first plural number of static random access memory (SRAM) calculators connected to the first plural number of DACs, among which a second number, which is one or more, of enabled SRAM calculators generate an analog convolution result signal through an analog operation between a weight and input data;
at least one analog-to-digital converter (ADC) connected to the first plural number of SRAM calculators and configured to convert the analog convolution result signal into digital convolution data; and
an analog PIM controller configured to output an enable control signal for enabling the second number, which is equal to or less than first plural number, of SRAM calculators among the first plural number of SRAM calculators to the first plural number of SRAM calculators on the basis of the convolution data output from the ADC.

2. The scalable analog PIM module of claim 1 , wherein the analog PIM controller outputs an enable signal for activating the second number of SRAM calculators among the first plural number of SRAM calculators to the second number of SRAM calculators and outputs a disable signal for deactivating other SRAM calculators among the first plural number of SRAM calculators to the other SRAM calculators, and
the disable signal stops the analog operation in the other SRAM calculators.

3. The scalable analog PIM module of claim 1 , wherein each of the SRAM calculators comprises:
an SRAM configured to store the weight;
a capacitor configured to store the analog input data through the connected DAC; and
a skip switch configured to control storage of the analog input data in the capacitor, and
when a value of the weight stored in the SRAM calculator is a specified first value, the analog PIM controller outputs an off-control signal for opening the skip switch of the SRAM calculator to the SRAM calculator to omit the analog operation of the SRAM calculator.

4. The scalable analog PIM module of claim 1 , wherein, when input data output from a sensor device (SD) ADC of a sensor signal processing part connected to the analog PIM module does not change a set number of times or more, the analog PIM controller increases an output resolution of the SD ADC and determines the second number of new SRAM calculators to be enabled among the first plural number of SRAM calculators according to the convolution data output from the ADC.

5. The scalable analog PIM module of claim 1 , wherein the analog PIM controller comprises:
an ADC output detector configured to detect the convolution data output from the ADC;
a comparator configured to compare the convolution data from the ADC output detector with previous convolution data; and
an ADC/SRAM enable controller configured to generate the enable control signal for enabling the second number of SRAM calculators determined from among the first plural number of SRAM calculators according to a comparison result of the comparator and output the enable control signal to the first plural number of SRAM calculators.

6. The scalable analog PIM module of claim 5 , wherein the ADC output detector further detects input data output from a sensor device (SD) ADC of a sensor signal processing part connected to the analog PIM module,
the comparator further compares the input data with previous input data, and
the ADC/SRAM enable controller outputs the enable control signal to the SD ADC to increase an output resolution of the SD ADC according to a comparison result of the input data and redetermines the second number of SRAM calculators to be enabled among the first plural number of SRAM calculators using the convolution data output from the ADC after the enable control signal is output to the SD ADC.

7. The scalable analog PIM module of claim 6 , wherein the analog PIM controller further comprises a memory configured to store the previous input data and previous convolution data.

8. The scalable analog PIM module of claim 5 , wherein, when the same result signal is consecutively received from the comparator a specified number of times or more, the ADC/SRAM enable controller outputs the enable control signal for enabling a second number, which is larger than the currently set second number, of SRAM calculators to the first plural number of SRAM calculators to increase a resolution of the analog operation of the first plural number of SRAM calculators.

9. The scalable analog PIM module of claim 5 , wherein the analog PIM controller outputs the weight and the input data adjusted according to a change of the second number based on the determination to the changed second number of SRAM calculators.

10. The scalable analog PIM module of claim 1 , wherein the analog PIM module is included in an integrated circuit.

11. A signal processing circuit comprising:
a power supply configured to generate power from an external signal;
a sensor signal processing part configured to process a sensing signal of a sensor; and
a convolutional neural network (CNN) control part configured to control the power supply and the sensor signal processing part according to workload data of the power generated by the power supply and sensing data generated by the sensor signal processing part,
wherein the CNN control part includes the scalable analog passive intermodulation (PIM) module of claim 1 .

12. The signal processing circuit of claim 11 , wherein the CNN control part generates and outputs a power control signal for controlling the power supply and a gain control signal for controlling gain of the sensor signal processing part from the workload data and the sensing data according to a CNN artificial intelligence technology employing the scalable analog PIM module.

13. The signal processing circuit of claim 11 , wherein the signal processing circuit is an integrated circuit.

14. A sensor device comprising:
the signal processing circuit of claim 11 ; and
a sensor connected to the signal processing circuit and configured to output a sensing signal to the signal processing circuit according to power supplied from the signal processing circuit.

15. A method of controlling analog passive intermodulation (PIM) comprising:
generating, by a second number, which is one or more, of enabled static random access memory (SRAM) calculators among a first plural number of SRAM calculators, an analog convolution result signal according to an analog operation between a weight and input data;
converting the analog convolution result signal into digital convolution data;
determining the second number of SRAM calculators to be enabled among the first plural number of SRAM calculators on the basis of the convolution data; and
enabling the determined second number of SRAM calculators.

16. The method of claim 15 , wherein the SRAM calculators comprise:
an SRAM configured to store the weight;
a capacitor configured to store the analog input data, and
a skip switch configured to control storage of the analog input data in the capacitor,
wherein the generating of the convolution result signal comprises omitting the analog operation through the skip switch according to an off-control signal received from the second number, which is one or more, of SRAM calculators.

17. The method of claim 15 , wherein the determining of the second number of SRAM calculators to be enabled comprises, when the convolution data is the same as previous convolution data a specified number of times or more, increasing the second number to increase a

Assignees

• Skaichips Co Ltd
• Research & Business Found Sungkyunkwan Univ
• Research &Business Foundation Sungkyunkwan Univ

Inventors

• Lee Kang Yoon
• Jo Jong Wan
• Byun Sung June
• Choi Dae Young
• Pu Young Gun
• Yoo Joon Mo
• Jung Yeon Jae
• Huh Hyung Ki
• Kim Seok Kee

Classifications

• H02M7/06

  using discharge tubes without control electrode or semiconductor devices without control electrode · CPC title

• H03G3/30

  in amplifiers having semiconductor devices · CPC title

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title

• H03M1/74

  Simultaneous conversion · CPC title

• H03M1/124

  Sampling or signal conditioning arrangements specially adapted for A/D converters · CPC title