Sampling and holding electrical signals with rail-to-rail equivalent output swing

Patent metadata

Field	Value
Publication number	US-12170509-B2
Application number	US-202318178394-A
Country	US
Kind code	B2
Filing date	Mar 3, 2023
Priority date	Mar 3, 2023
Publication date	Dec 17, 2024
Grant date	Dec 17, 2024

Abstract

A sample and hold circuit providing rail-to rail equivalent output is described. The circuit includes a sample and hold amplifier containing two separate sets of sampling capacitors, one set is coupled to a PMOS transistor differential stage and the other set is coupled to an NMOS transistor differential stage. The differential stages drive a current mirror based push-pull output differential stage to provide an output signal with ranges equivalent to a rail-to rail output signal swing.

First claim

I claim:

1. A circuit for sampling and holding electrical signals comprising:
a sample and hold amplifier comprising:
a first input node;
a first output node;
at least two capacitors, where each capacitor of the at least two capacitors comprises a bottom plate and a top plate, where each respective top plate is coupled to the first input node and the first output node;

a first PMOS transistor comprising:
a gate node connected to a bottom plate of a first capacitor of the at least two capacitors; and
a drain node coupled to an input node of a first current mirror, where an output of the first current mirror is coupled to a second output node of the sample and hold amplifier; and

a first NMOS transistor comprising:
a gate node connected to a bottom plate of a second capacitor of the at least two capacitors; and
a drain node coupled to an input node of a second current mirror, where an output of the second current mirror is coupled to the second output node of the sample and hold amplifier.

2. The circuit of claim 1 , wherein the gate node of the first PMOS transistor and the bottom plate of the first capacitor are coupled to a first source of bias voltage via a first switch, and wherein the gate node of the first NMOS transistor and the bottom plate of the second capacitor are coupled to a second source of bias voltage via a second switch.

3. The circuit of claim 1 , further comprising:
at least two additional capacitors, wherein each respective capacitor of the at least two additional capacitors comprises:
a bottom plate connected to a respective bottom plate of one of the at least two capacitors; and
a top plate coupled to at least one voltage source and coupled to the first input node of the sample and hold amplifier.

4. The circuit of claim 1 , wherein the first current mirror and the second current mirror are disabled during a tracking mode of operation of the circuit.

5. The circuit of claim 1 , wherein the sample and hold amplifier further comprises:
a second input node;
at least two additional capacitors,
wherein each capacitor of the at least two additional capacitors comprises a top plate, where each respective top plate is coupled to the second input node and the second output node; and

wherein the circuit further comprises:
a second PMOS transistor comprising:
a source node coupled to a source node of the first PMOS transistor;
a gate node connected to the bottom plate of a first capacitor of the at least two additional capacitors; and
a drain node coupled to an input node of a third current mirror, wherein an output of the third current mirror is coupled to the first output node; and

a second NMOS transistor comprising:
a source node coupled to a source node of the first NMOS transistor;
a gate node connected to a bottom plate of a second capacitor of the at least two additional capacitors; and
a drain node coupled to an input node of a fourth current mirror, wherein an output of the fourth current mirror is coupled to the first output node.

6. The circuit of claim 5 , wherein the gate node of the first PMOS transistor and the gate node of the second PMOS transistor are coupled together with a first switch, wherein the first switch is closed during a tracking mode of operation of the circuit, wherein the first switch is open during a holding mode of operation of the circuit, and
wherein the gate node of the first NMOS transistor and the gate node of the second NMOS transistor are coupled together with a second switch, wherein the second switch is closed during the tracking mode, and wherein the second switch is open during the holding mode.

7. The circuit of claim 5 further comprising:
a set of four additional capacitors, wherein each capacitor of the set of four additional capacitors comprises:
a bottom plate connected to the bottom plate of a respective one of the at least two capacitors and the at least two additional capacitors; and
a top plate coupled to an input node and coupled to at least one voltage source.

8. The circuit of claim 7 , wherein each respective top plate of the set of four additional capacitors is coupled to one of two different voltage sources.

9. The circuit of claim 7 , wherein a voltage value produced by the voltage source is different from an amplifier input common mode voltage.

10. The circuit of claim 5 , wherein the source node of the first PMOS transistor and the source node of the second PMOS transistor are coupled to an invariant current source, and wherein the source node of the first NMOS transistor and the source node of the second NMOS transistor are coupled to a controlled current source, and wherein the controlled current source controls an amplifier output common mode during a tracking mode of operation.

11. The circuit of claim 5 , wherein the source node of the first NMOS transistor and the source node of the second NMOS transistor are coupled to an invariant current source, wherein the source node of the first PMOS transistor and the source node of the second PMOS transistor are coupled to a controlled current source, and wherein the controlled current source controls an amplifier output common mode during a tracking mode of operation of the circuit.

12. A method for sampling and holding an electrical signal:
at first time enabling a tracking mode in a sample and hold amplifier by:
shunting together gate nodes of an NMOS transistor differential stage and shunting together gate nodes of a PMOS transistor differential stage using a first set of switches;
coupling together top plates from a set of sampling capacitors to at least one input node of the sample and hold amplifier, where bottom plates of the set of sampling capacitors are connected to different gate nodes of the NMOS and PMOS transistor differential stages;
disabling a first set of PMOS current mirrors driven by the NMOS transistor differential stage; and
disabling a first set of NMOS current mirrors driven by the PMOS transistor differential stage; and

at second time enabling a holding mode in the sample and hold amplifier by:
opening the first set of switches and second set of switches,
disconnecting the set of sampling capacitors from the at least one input node;
enabling the first set of PMOS current mirrors;
enabling the first set of NMOS current mirrors;
coupling a first subset of the first set of sampling capacitors to at least one output of the sample and hold amplifier to provide a holding output signal; and
coupling a second subset of the sampling capacitors to at least one voltage source.

13. The method of claim 12 , wherein during the tracking mode, the gate nodes of the NMOS transistor differential stage and the gate nodes of the PMOS transistor differential stage are coupled to different sources of a bias voltage.

14. The method of claim 12 , wherein a voltage value generated by the at least one voltage source, to which the second subset of the sampling capacitors is connected in the holding mode, is different from an input common mode voltage of the sample and hold amplifier to facilitate a control of an amplifier output common mode voltage in holding mode.

15. The method of claim 12 , wherein in the holding mode, the sampling capacitors of the second subset are connected to different voltage sources to compensate an offset voltage of the sample and hold amplifier.

16. The method of claim 15 , wherein a common mode voltage generated by different voltage sources is different from an input common mode voltage of the sample and hold amplifier to facilitate a control of an amplifier output common mode volta

Assignees

• Cisco Tech Inc

Inventors

• Zabroda Oleksiy

Classifications

• G11C27/026

  associated with an amplifier (G11C27/028 takes precedence) · CPC title

• H03F3/4521

  Complementary long tailed pairs having parallel inputs and being supplied in parallel · CPC title

• H03F3/45932

  by using feedback means (H03F3/45968 takes precedence) · CPC title

• H03F3/45995

  using switching means · CPC title

• H03F3/45991

  by using balancing means · CPC title