Array substrate, display panel, and display device

Patent metadata

Field	Value
Publication number	US-12170287-B2
Application number	US-202017418811-A
Country	US
Kind code	B2
Filing date	Dec 9, 2020
Priority date	Dec 19, 2019
Publication date	Dec 17, 2024
Grant date	Dec 17, 2024

Abstract

Provided is an array substrate, including: a display region including signal lines and a peripheral region including a bonding region; wherein the bonding region includes at least one row of signal line input terminals disposed on a first substrate, the signal line input terminals being electrically connected to the signal lines; and the signal line input terminal includes an etched conductive layer, at least the etched conductive layers in two adjacent signal line input terminals disposed in a same row being disposed on different layers.

First claim

What is claimed is:

1. An array substrate, comprising: a display region comprising signal lines, a peripheral region comprising a bonding region, and signal line leads disposed in the peripheral region; wherein
the bonding region comprises at least two rows of signal line input terminals disposed on a first substrate, the signal line input terminals being electrically connected to the signal lines;
the signal line input terminal comprises an etched conductive layer, at least the etched conductive layers in two adjacent signal line input terminals disposed in a same row being disposed on different layers; and
one end of each of the signal line leads is electrically connected to the signal line and the other end of each of the signal line leads is electrically connected to the signal line input terminal; parts, proximal to the signal line input terminals, of two adjacent signal line leads are disposed on different layers; and an orthogonal projection of the signal line lead electrically connected to a first signal line input terminal onto the first substrate falls between orthogonal projections of the two adjacent signal line input terminals in an adjacent row of signal line input terminals onto the first substrate, wherein the first signal line input terminal being any one of one row of signal line input terminals and the adjacent rows of signal line input terminals being disposed between the first signal line input terminal and the display region.

2. The array substrate according to claim 1 , wherein the signal line input terminal comprises a single metal layer, and the etched conductive layer is the metal layer.

3. The array substrate according to claim 1 , wherein the signal line input terminal comprises a single metal layer and a single metal oxide layer, and the etched conductive layer is the metal layer.

4. The array substrate according to claim 1 , wherein the signal line lead and at least the etched conductive layer in the signal line input terminal electrically connected to the signal line lead are disposed on different layers.

5. The array substrate according to claim 1 , wherein the bonding region comprises three rows of the signal line input terminals, the signal line input terminals in a first row, the signal line input terminals in a second row and the signal line input terminals in a third row being arranged in sequence in a direction from the display region to the peripheral region; wherein
a first signal line lead projection and a second signal line lead projection are respectively disposed on both sides of a center line of the orthogonal projection of the signal line input terminals in the second row onto the first substrate, the center line extending in the direction from the display region to the peripheral region, the first signal line lead projection being an orthogonal projection of the signal line lead electrically connected to the signal line input terminal in the second row onto the first substrate, and the second signal line lead projection being an orthogonal projection of the signal line lead electrically connected to the signal line input terminal in the third row onto the first substrate;
wherein a spacing from the first signal line lead projection to the center line is less than a spacing from the first signal line lead projection to an orthogonal projection of the signal line input terminal in the first row, closest to the first signal line lead projection, onto the first substrate, and a spacing from the second signal line lead projection to the center line is less than a spacing from the second signal line lead projection to an orthogonal projection of the signal line input terminal in the first row, closest to the second signal line lead projection, onto the first substrate.

6. The array substrate according to claim 1 , wherein the bonding region comprises three rows of the signal line input terminals, the signal line input terminals in a first row, the signal line input terminals in a second row and the signal line input terminals in a third row being arranged in sequence in a direction from the display region to the peripheral region; wherein
a first signal line lead projection and a second signal line lead projection are respectively disposed on both sides of a center line of the orthogonal projection of the signal line input terminals in the second row onto the first substrate, the center line extending in the direction from the display region to the peripheral region, the first signal line lead projection being an orthogonal projection of the signal line lead electrically connected to the signal line input terminal in the second row onto the first substrate, and the second signal line lead projection being an orthogonal projection of the signal line lead electrically connected to the signal line input terminal in the third row onto the first substrate;
wherein a spacing between a third signal line lead projection and the first signal line lead projection is less than a spacing between the first signal line lead projection and the second signal line lead projection; and a spacing from the second signal line lead projection to an orthogonal projection of the signal line input terminal in the first row, closest to the second signal line lead projection, onto the first substrate is less than the spacing between the first signal line lead projection and the second signal line lead projection, the third signal line lead projection being an orthogonal projection of the signal line lead electrically connected to the signal line input terminal in the first row onto the first substrate.

7. The array substrate according to claim 1 , further comprising: an anti-static wire; and each of the signal lines is electrically connected to the anti-static wire by at least one anti-static switch.

8. The array substrate according to claim 7 , wherein the array substrate further comprises a common electrode line;
wherein the common electrode line is electrically connected to the anti-static wire by at least one anti-static switch.

9. The array substrate according to claim 1 , wherein the signal line comprises a plurality of first sub-signal lines arranged in a first direction and extending in a second direction, and a plurality of second sub-signal lines arranged in the second direction and extending in the first direction, the first direction being intersected with the second direction; and
the signal line input terminal comprises a first sub-signal line input terminal and a second sub-signal line input terminal, the first sub-signal line input terminal being electrically connected to the first sub-signal line and the second sub-signal line input terminal being electrically connected to the second sub-signal line.

10. The array substrate according to claim 9 , wherein
the first sub-signal line is a data line, and the second sub-signal line is a gate line;
the first sub-signal line input terminal is a data line input terminal, and the second sub-signal line input terminal is a gate line input terminal; and
the bonding region comprises at least one of:
at least two rows of data line input terminals and at least two rows of gate line input terminals.

11. A display panel comprising an array substrate, wherein the array substrate comprises a display region comprising signal lines, a peripheral region comprising a bonding region, and signal line leads disposed in the peripheral region; wherein
the bonding region comprises at least one row of signal line input terminals disposed on a first substrate, the signal line input terminals being electrically connected to the signal lines;
the signal line input terminal comprises an etched conductive layer, at least the etched conductive layers

Assignees

• Beijing Boe Technology Dev Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Ma Yongda
• Qiao Yong
• Xian Jianbo

Classifications

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• G02F1/1345

  Conductors connecting electrodes to cell terminals · CPC title

• G02F1/1362

  Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)} · CPC title