Methods of forming bottom dielectric isolation layers

Patent metadata

Field	Value
Publication number	US-12170230-B2
Application number	US-202117531726-A
Country	US
Kind code	B2
Filing date	Nov 20, 2021
Priority date	Aug 8, 2021
Publication date	Dec 17, 2024
Grant date	Dec 17, 2024

Abstract

Embodiments of this disclosure relate to methods for removing a dummy material from under a superlattice structure. In some embodiments, after removing the dummy material, it is replaced with a bottom dielectric isolation layer beneath the superlattice structure.

First claim

What is claimed is:

1. A processing method for removing a dummy material, the method comprising:
forming a liner over a superlattice structure on a dummy material, the superlattice structure comprising a plurality of channel layers and a corresponding plurality of semiconductor material layers alternatingly arranged in a plurality of stacked pairs extending between a source trench and a drain trench, the semiconductor material layers comprising silicon (Si), the channel layers comprising of silicon-germanium (SiGe), and the dummy material comprising silicon doped with a dopant selected from one or more of boron, phosphorus, arsenic, or germanium, the concentration of dopant in a range of from 2 atomic percent to 10 atomic percent;
removing the liner from the dummy material; and
removing the dummy material without substantially affecting the channel layers and the semiconductor material layers covered by the liner.

2. The method of claim 1 , wherein the liner comprises silicon nitride (SiN), silicon oxide (SiO), silicon carbide (SiC), or a combination thereof.

3. The method of claim 1 , wherein removing the liner comprises a directional etch process.

4. The method of claim 1 , wherein removing the dummy material comprises a selective etch process that is selective to the dummy material over the liner.

5. The method of claim 1 , wherein removing the dummy material comprises a selective etch process that is selective to the dummy material over the channel layer or the semiconductor material layer adjacent to the dummy material.

6. The method of claim 1 , further comprising depositing a bottom dielectric isolation layer beneath the superlattice structure after removing the dummy material.

7. The method of claim 6 , wherein the bottom dielectric isolation layer is deposited by a flowable deposition process.

8. The method of claim 6 , wherein the bottom dielectric isolation layer comprises silicon oxide.

9. A processing method comprising:
recessing a plurality of channel layers in a superlattice structure to remove a depth of channel material and form a plurality of recessed channel layers, the superlattice structure on a dummy material, the superlattice structure comprising the plurality of channel layers and a corresponding plurality of semiconductor material layers alternatingly arranged in a plurality of stacked pairs extending between a source trench and a drain trench, the plurality of semiconductor material layers comprising silicon (Si), the plurality of channel layers comprising silicon-germanium (SiGe), and the dummy material comprising silicon doped with a dopant selected from one or more of boron, phosphorus, arsenic, or germanium, the concentration of dopant in a range of from 2 atomic percent to 10 atomic percent;
forming a conformal liner having a thickness over the plurality of recessed channel layers, the plurality of semiconductor material layers and the dummy material;
removing the liner from the dummy material without exposing the plurality of recessed channel layers or the plurality of semiconductor material layers;
removing the dummy material;
etching the liner to expose the plurality of semiconductor material layers;
depositing a bottom dielectric isolation layer under the superlattice structure; and
depositing a silicon material on the bottom dielectric isolation layer to fill the superlattice structure.

10. The method of claim 9 , wherein a total thickness of the superlattice structure is in a range of about 30 nm to about 80 nm.

11. The method of claim 9 , wherein the superlattice structure comprises 3 to 5 pairs of channel layers and semiconductor material layers.

12. The method of claim 9 , wherein each of the channel layers and the semiconductor material layers has a thickness in a range of in a range of about 4 nm to about 10 nm.

13. The method of claim 9 , wherein a lateral distance between the source trench and the drain trench is in a range of about 20 nm to about 60 nm.

14. The method of claim 9 , wherein the depth of channel material removed from the plurality of channel layers is in a range of about 5 nm to about 10 nm.

15. The method of claim 9 , wherein the thickness of the liner is in a range of about 3 nm to about 5 nm.

Assignees

• Applied Materials Inc

Inventors

• Lin Sankuei
• Subrahmanyan Pradeep K

Classifications

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10D84/038 Primary

  using silicon technology, e.g. SiGe · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title