Software Vsync filtering

Patent metadata

Field	Value
Publication number	US-12170071-B2
Application number	US-202418424699-A
Country	US
Kind code	B2
Filing date	Jan 26, 2024
Priority date	Dec 31, 2019
Publication date	Dec 17, 2024
Grant date	Dec 17, 2024

Abstract

Methods and apparatuses are provided for alignment of hardware and software Vsync signals through filtering out delayed timestamp signals in a hardware timestamp signal used to generate the software Vsync. The alignment may occur when a display client is operating in a video mode but not a command mode. A compositor or processing unit may receive a hardware Vsync signal from a display using a video mode, generate a hardware timestamp signal based on the hardware Vsync signal, determine a delay for a pulse in the hardware timestamp signal based on a delay for a set of previous frames, determine whether the delay for the pulse is over a threshold, and control rendering and transmission of a frame to the display based on the delay for the pulse being over the threshold. Thus, accurate Vsync signal synchronization may occur.

First claim

What is claimed is:

1. A method of display processing, comprising:
receiving a hardware Vsync signal from a display using a video mode;
generating a hardware timestamp signal based on the hardware Vsync signal;
determining a delay for a pulse in the hardware timestamp signal based on a delay for a set of previous frames;
determining whether the delay for the pulse is over a threshold; and
controlling rendering and transmission of a frame to the display based on the delay for the pulse being over the threshold.

2. The method of claim 1 , wherein the determining the delay for the pulse is based on a statistic of the delay for the set of previous frames.

3. The method of claim 1 , wherein the determining whether the delay for the pulse is over the threshold is based on the display not using a command mode.

4. The method of claim 3 , wherein the video mode is a mode in which pixels are transmitted to the display to be displayed, and the command mode is a mode in which data is transmitted to the display to render pixels to be displayed based on the data.

5. The method of claim 1 , wherein the delay for the pulse is an amount of time between reception of the hardware Vsync signal and inclusion of the pulse in the hardware timestamp signal.

6. The method of claim 1 , wherein the determining the delay for the pulse is based on a determination that the display uses the video mode.

7. The method of claim 1 , wherein the determining whether the delay for the pulse is over the threshold is based on a determination that the display uses the video mode.

8. The method of claim 1 , wherein the display is determined to use the video mode based on a determination that the delay for the pulse is over the threshold.

9. An apparatus for display processing, comprising:
one or more memories; and
one or more processors each coupled to at least one of the one or more memories, the one or more processors, individually or in combination, configured to:
receive a hardware Vsync signal from a display using a video mode;
generate a hardware timestamp signal based on the hardware Vsync signal;
determine a delay for a pulse in the hardware timestamp signal based on a delay for a set of previous frames;
determine whether the delay for the pulse is over a threshold; and
control rendering and transmission of a frame to the display based on the delay for the pulse being over the threshold.

10. The apparatus of claim 9 , wherein the one or more processors, individually or in combination, are configured to determine the delay for the pulse based on a statistic of the delay for the set of previous frames.

11. The apparatus of claim 9 , wherein the one or more processors, individually or in combination, are configured to determine whether the delay for the pulse is over the threshold based on the display not using a command mode.

12. The apparatus of claim 11 , wherein the video mode is a mode in which pixels are transmitted to the display to be displayed, and the command mode is a mode in which data is transmitted to the display to render pixels to be displayed based on the data.

13. The apparatus of claim 9 , wherein the delay for the pulse is an amount of time between reception of the hardware Vsync signal and inclusion of the pulse in the hardware timestamp signal.

14. The apparatus of claim 9 , wherein the one or more processors, individually or in combination, are configured to determine the delay for the pulse based on a determination that the display uses the video mode.

15. The apparatus of claim 9 , wherein the one or more processors, individually or in combination, are configured to determine whether the delay for the pulse is over the threshold based on a determination that the display uses the video mode.

16. The apparatus of claim 9 , wherein the display is determined to use the video mode based on a determination that the delay is over the threshold.

17. An apparatus for display processing, comprising:
one or more memories; and
one or more processors each coupled to at least one of the one or more memories, the one or more processors, individually or in combination, configured to:
receive a hardware Vsync signal from a display using a video mode;
generate a hardware timestamp signal based on the hardware Vsync signal;
determine a delay for a pulse in the hardware timestamp signal based on a statistic of a delay for a set of previous frames, the delay for the pulse being an amount of time between reception of the hardware Vsync signal and inclusion of the pulse in the hardware timestamp signal;
determine whether the delay for the pulse is over a threshold; and
control rendering and transmission of a frame to the display based on the delay for the pulse being over the threshold.

18. The apparatus of claim 17 , wherein the one or more processors, individually or in combination, are configured to determine whether the delay for the pulse is over the threshold based on the display not using a command mode.

19. The apparatus of claim 18 , wherein the video mode is a mode in which pixels are transmitted to the display to be displayed, and the command mode is a mode in which data is transmitted to the display to render pixels to be displayed based on the data.

20. The apparatus of claim 17 , wherein the one or more processors, individually or in combination, are configured to determine the delay for the pulse based on a determination that the display uses the video mode.

Assignees

• Qualcomm Inc

Inventors

• Zhang Nan
• Han Long
• Xu Yongjun

Classifications

• G09G5/18

  Timing circuits for raster scan displays (specially adapted for television H04N {; synchronisation between the display unit and other display units, videodisc player G09G5/12}) · CPC title

• G09G2340/0435

  Change or adaptation of the frame rate of the video stream · CPC title

• G09G2360/18

  Use of a frame buffer in a display terminal, inclusive of the display panel · CPC title

• G09G5/005 Primary

  Adapting incoming signals to the display format of the display terminal · CPC title

• G09G2360/08

  Power processing, i.e. workload management for processors involved in display operations, such as CPUs or GPUs · CPC title