Clock generating circuit and method for trimming period of oscillator clock signal

Patent metadata

Field	Value
Publication number	US-12169419-B2
Application number	US-202217841078-A
Country	US
Kind code	B2
Filing date	Jun 15, 2022
Priority date	Jun 17, 2021
Publication date	Dec 17, 2024
Grant date	Dec 17, 2024

Abstract

A clock generating circuit includes an oscillator, a clock counter, a finite state machine, and a non-volatile memory. The oscillator outputs an oscillator clock signal having a period based on a trim value. The clock counter counts the oscillator clock signal for a reference time. The finite state machine obtains the count value of the counted oscillator clock signal from the clock counter, and in a test mode, compares the count value with a target count value and changes the trim value based on the comparison result and determines a final trim value based on the changed trim value. The non-volatile memory stores the final trim value that is determined.

First claim

What is claimed is:

1. A clock generating circuit comprising:
an oscillator configured to output an oscillator clock signal having a period based on a trim value;
a clock counter configured to count the oscillator clock signal for a reference time;
a finite state machine configured to obtain, from the clock counter, a count value of the oscillator clock signal that is counted, and in a test mode, compare the count value with a target count value and change the trim value based on a comparison result and determine a final trim value based on the trim value that is changed; and
a non-volatile memory that stores the final trim value that is determined,
wherein the oscillator is configured to output the oscillator clock signal having a shorter period as the trim value decreases.

2. The clock generating circuit of claim 1 , wherein the finite state machine is further configured to:
reduce the count value by stepwisely increasing the trim value, when the count value is greater than the target count value; and
increase the count value by stepwisely reducing the trim value, when the count value is less than or equal to the target count value.

3. The clock generating circuit of claim 2 , wherein the finite state machine is further configured to:
determine a trim value corresponding to the count value that exceeds the target count value as the final trim value when the count value exceeds the target count value as the count value increases; and
determine a trim value corresponding to the count value that is less than the target count value as the final trim value when the count value is less than the target count value as the count value decreases.

4. The clock generating circuit of claim 2 , wherein the finite state machine is further configured to determine, as the final trim value, a trim value corresponding to a value that is closest to the target count value among count values that exceed the target count value.

5. The clock generating circuit of claim 3 , wherein the finite state machine is further configured to store, in the non-volatile memory, the final trim value that is determined, and
the oscillator is further configured to output the oscillator clock signal having a period based on the final trim value that is stored.

6. The clock generating circuit of claim 1 , wherein the finite state machine is further configured to, in a verify mode, determine whether the count value for the oscillator clock signal having the period based on the final trim value is less than an upper limit and greater than a lower limit, and output a determination result to a test device.

7. The clock generating circuit of claim 1 , wherein the finite state machine is further configured to, in a manual trim mode, output the count value to a test device.

8. The clock generating circuit of claim 1 , wherein the finite state machine is further configured to receive a test clock signal that is independent of the oscillator clock signal, and cause the clock counter to operate for the reference time according to the test clock signal.

9. A system comprising:
a plurality of chips in a wafer, each chip comprising:
a clock generating circuit comprising an oscillator configured to output an oscillator clock signal having a period based on a trim value;
a clock counter configured to count the oscillator clock signal for a reference time;
a finite state machine configured to obtain, from the clock counter, a count value of the oscillator clock signal that is counted, and in a test mode, compare the count value with a target count value and change the trim value based on a comparison result and determine a final trim value based on the trim value that is changed; and
a non-volatile memory that stores the final trim value that is determined; and

a test device configured to test one or more of the plurality of chips,
wherein the plurality of chips are connected in parallel to the test device.

10. The system of claim 9 , wherein the finite state machine is further configured to:
stepwisely increase the trim value when the count value is greater than the target count value; and
stepwisely reduce the trim value when the count value is less than the target count value, and
the oscillator is further configured to output the oscillator clock signal having a shorter period as the trim value decreases.

11. The system of claim 10 , wherein the finite state machine is further configured to:
determine, as the final trim value, the trim value corresponding to a time when the count value starts to be greater than the target count value as the count value increases, when the trim value decreases stepwisely; and
determine, as the final trim value, the trim value corresponding to a time immediately before the count value starts to be greater than the target count value as the count value decreases, when the trim value increases stepwisely.

12. The system of claim 11 , wherein the finite state machine is further configured to store, in the non-volatile memory, the final trim value that is determined, and
the oscillator is further configured to output the oscillator clock signal having a period based on the final trim value that is stored.

13. The system of claim 9 , wherein the test device is configured to set the finite state machine to operate in any one of the test mode, a verify mode, and a manual trim mode.

14. The system of claim 13 , wherein the finite state machine is configured to execute the test mode and, in the verify mode that is executed after the test mode is executed, determine whether the count value for the oscillator clock signal having the period based on the final trim value is less than an upper limit and greater than a lower limit, and output a determination result to the test device, and
the test device is configured to determine that trimming of the period of the oscillator clock signal in the test mode was successful, when it is determined that the count value is less than the upper limit and greater than the lower limit.

15. The system of claim 13 , wherein the finite state machine is further configured to, in the manual trim mode, output the count value to the test device, and
the test device is configured to obtain the period of the oscillator clock signal, based on the count value that is output.

16. The system of claim 9 , wherein the test device is configured to output a test clock signal to the finite state machine, the test clock signal having a period that is different from the period of the oscillator clock signal.

17. The system of claim 9 , wherein the test device is configured to, for each of the plurality of chips, output, to the finite state machine of the chip, a target count value,
wherein the target count values differ with the period of the oscillator clock signal for each of the plurality of chips.

18. A method comprising:
outputting, by an oscillator, an oscillator clock signal having a period based on a trim value;
counting, by a clock counter, the oscillator clock signal for a reference time; and
obtaining, by a finite state machine, a count value for the oscillator clock signal that is counted, and in a test mode, comparing the count value with a target count value and changing the trim value based on a comparison result and determining a final trim value based on the trim value that is changed,
wherein the outputting of the oscillator clock signal comprises outputting the oscillator clock signal having a shorter period as the trim value decreases.

19. The method of claim 18 , wherein the determining of

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hyunil
• Kang Jisu
• Park Taewook
• Choi Hongmook

Classifications

• H03K21/38

  Starting, stopping or resetting the counter (counters with a base other than a power of two H03K23/48, H03K23/66) · CPC title

• G11C29/56004

  Pattern generation · CPC title

• G11C29/023 Primary

  in clock generator or timing circuitry · CPC title

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title