Pixel unit and driving method therefor, array substrate, and vertical alignment liquid crystal display device

Patent metadata

Field	Value
Publication number	US-12169344-B2
Application number	US-202117798170-A
Country	US
Kind code	B2
Filing date	Sep 16, 2021
Priority date	Oct 29, 2020
Publication date	Dec 17, 2024
Grant date	Dec 17, 2024

Abstract

A pixel unit includes: a first insulating layer; a first pixel electrode located on a first side of the first insulating layer and including a plurality of first electrode strips; a common electrode located on the first side of the first insulating layer and including a plurality of second electrode strips, the second electrode strips and the first electrode strips being sequentially and alternately arranged in a first direction, and slits each being disposed between a second electrode strip in the second electrode strips and a first electrode strip in the first electrode strips that are adjacent to each other; and a second pixel electrode located on a second side of the first insulating layer. The second side of the first insulating to layer is opposite to the first side of the first insulating layer. The second pixel electrode is overlapped with at least a region where the slits are located.

First claim

What is claimed is:

1. A pixel unit, comprising:
a first insulating layer;
a first pixel electrode located on a first side of the first insulating layer and including a plurality of first electrode strips;
a common electrode located on the first side of the first insulating layer and including a plurality of second electrode strips; wherein the second electrode strips and the first electrode strips are sequentially and alternately arranged in a first direction; and slits each are disposed between a second electrode strip in the second electrode strips and a first electrode strip in the first electrode strips that are adjacent to each other; and
a second pixel electrode located on a second side of the first insulating layer; wherein the second side of the first insulating layer is opposite to the first side of the first insulating layer; and the second pixel electrode is overlapped with at least a region where the slits are located;
wherein each of the plurality of first electrode strips includes at least two first electrode segments connected in sequence; and two adjacent first electrode segments have a first included angle therebetween, and the first included angle is greater than 0 degree and less than 180 degrees; and each of the plurality of second electrode strips includes at least two second electrode segments connected in sequence; and two adjacent second electrode segments have a second included angle therebetween, and the second included angle is greater than 0 degree and less than 180 degrees;
wherein a plane perpendicular to the first insulating layer and perpendicular to the first direction is a reference plane; wherein an included angle between each of at least one first electrode segment and the reference plane is 45±7 degrees, and an included angle between each of at least one second electrode segment and the reference plane is 45±7 degrees;
the pixel unit further comprises:
a first thin film transistor located on the second side of the first insulating layer; wherein a control electrode of the first thin film transistor is configured to be coupled to a scan signal line, a first electrode of the first thin film transistor is configured to be coupled to a first data voltage line, and a second electrode of the first thin film transistor is coupled to the plurality of first electrode strips of the first pixel electrode; and
a second thin film transistor located on the second side of the first insulating layer; wherein a control electrode of the second thin film transistor is configured to be coupled to the scan signal line, a first electrode of the second thin film transistor is configured to be coupled to a second data voltage line, and a second electrode of the second thin film transistor is coupled to the second pixel electrode; wherein
the common electrode is configured to be coupled to a common voltage line; and
the second pixel electrode includes a planar electrode and a third conductive connection portion, and the planar electrode is located on a side of a gate insulating layer of the second thin film transistor away from the first insulating layer; the gate insulating layer includes a fourth via; and the third conductive connection portion is connected to the second electrode of the second thin film transistor, and is connected to the planar electrode through the fourth via.

2. The pixel unit according to claim 1 , wherein
the first insulating layer includes a first via; and
the first pixel electrode further includes a first conductive connection portion; and the first conductive connection portion is connected to the plurality of first electrode strips, and is connected to the second electrode of the first thin film transistor through the first via.

3. The pixel unit according to claim 1 , wherein
the gate insulating layer of the second thin film transistor further includes a second via; the first insulating layer includes a third via exposing the second via; and
the common electrode further includes a second conductive connection portion; and the second conductive connection portion is connected to the plurality of second electrode strips, and is connected to the common voltage line through the second via and the third via.

4. The pixel unit according to claim 1 , wherein
a width of a slit in the slits in the first direction is greater than or equal to 6.6 μm, and is less than or equal to 7.3 μm.

5. A driving method of the pixel unit according to claim 1 , comprising:
applying a common voltage to the common electrode, and applying pixel voltages having a same magnitude and opposite polarities to the first pixel electrode and the second pixel electrode, respectively, so as to drive the pixel unit.

6. The driving method according to claim 5 , further comprising:
switching the pixel voltages respectively applied to the first pixel electrode and the second pixel electrode to each other, and repeating this step.

7. An array substrate having a plurality of pixel regions, the array substrate comprising:
a plurality of pixel units according to claim 1 ;
a plurality of scan signal lines extending in the first direction;
a plurality of common voltage lines extending in the first direction;
a plurality of first data voltage lines extending in a second direction intersecting the first direction; and
a plurality of second data voltage lines extending in the second direction; wherein each pixel region is defined by a second data voltage line, a scan signal line, a common voltage line, and a first data voltage line; and the pixel region is provided with a pixel unit in the plurality of pixel units therein.

8. A vertical alignment liquid crystal display device, comprising:
the array substrate according to claim 7 ;
a color filter substrate arranged opposite to the array substrate; and
a liquid crystal layer disposed between the array substrate and the color filter substrate.

9. The vertical alignment liquid crystal display device according to claim 8 , further comprising:
a first polarizer located on a side of the color filter substrate away from the liquid crystal layer; and
a second polarizer located on a side of the array substrate away from the liquid crystal layer;
wherein one of a polarization direction of the first polarizer and a polarization direction of the second polarizer is parallel to the first direction, and another one of the polarization direction of the first polarizer and the polarization direction of the second polarizer is perpendicular to the first direction.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Choi Hyunsic

Classifications

• G02F1/13624

  having more than one switching element per pixel · CPC title

• G02F1/134363

  for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS] · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/136222

  Colour filters incorporated in the active matrix substrate · CPC title

• G02F1/134372

  for fringe field switching [FFS] where the common electrode is not patterned · CPC title