Display device

Patent metadata

Field	Value
Publication number	US-12167651-B2
Application number	US-202117533563-A
Country	US
Kind code	B2
Filing date	Nov 23, 2021
Priority date	Dec 28, 2020
Publication date	Dec 10, 2024
Grant date	Dec 10, 2024

Abstract

A display device includes a substrate on which a display area including a plurality of pixels and a non-display area surrounding the display area are defined, a first voltage line disposed on the substrate in the non-display area, where the first voltage line provides a first voltage to the pixels, a second voltage line disposed on the substrate in the non-display area, where the second voltage line provides a second voltage to the pixels, and a first demux circuit area and a second demux circuit area disposed on the substrate in the non-display area, where the first demux circuit area and the second demux circuit area transmit data signals to the pixels. The first voltage line passes an area between the first demux circuit area and the second demux circuit area.

First claim

What is claimed is:

1. A display device comprising:
a substrate on which a display area including a plurality of pixels and a non-display area surrounding the display area are defined;
a first voltage line disposed on the substrate in the non-display area, wherein the first voltage line provides a first voltage to the pixels;
a second voltage line disposed on the substrate in the non-display area, wherein the second voltage line provides a second voltage to the pixels; and
a first demux circuit area and a second demux circuit area disposed on the substrate in the non-display area, wherein the first demux circuit area and the second demux circuit area transmit data signals to the pixels, and
wherein the first voltage line passes an area between the first demux circuit area and the second demux circuit area.

2. The display device of claim 1 , wherein the display area has a circular shape.

3. The display device of claim 1 , further comprising:
a first voltage bypass line connected to the first voltage line and disposed along an edge of the display area; and
a second voltage bypass line connected to the second voltage line and disposed along the edge of the display area.

4. The display device of claim 1 , wherein
the first voltage is an initialization voltage, and
the second voltage is a low power supply voltage.

5. The display device of claim 1 , wherein
the first voltage is a low power voltage, and
the second voltage is an initialization voltage.

6. The display device of claim 1 , wherein the first demux circuit area and the second demux circuit area are disposed to be spaced apart in one direction.

7. The display device of claim 1 , further comprising:
a third voltage line disposed on the substrate in the non-display area, wherein the third voltage line provides a third voltage to the pixels.

8. The display device of claim 7 , wherein the third voltage is a high power voltage.

9. The display device of claim 7 , wherein a part of the third voltage line passes the area between the first demux circuit area and the second demux circuit area.

10. The display device of claim 9 , wherein a width of the part of the third voltage line is narrower than a width of another part of the third voltage line connected to the part.

11. The display device of claim 1 , further comprising:
a plurality of voltage output lines connected to the first voltage line.

12. The display device of claim 11 , wherein
some of the voltage output lines partially overlap the first demux circuit area, and
others of the voltage output lines partially overlap the second demux circuit area.

13. The display device of claim 11 , further comprising:
a voltage transmission line connected to the first voltage line, and
wherein at least some of the voltage output lines are connected to the first voltage line by the voltage transmission line.

14. The display device of claim 13 , wherein
some of the voltage transmission lines overlap the first demux circuit area, and
others of the voltage transmission lines overlap the second demux circuit area.

15. The display device of claim 13 , wherein the first voltage line and the voltage output line are disposed in different layers from each other.

16. The display device of claim 11 , wherein the plurality of voltage output lines are disposed in a same layer as each other.

17. The display device of claim 11 , wherein at least some of the plurality of voltage output lines are disposed in different layers from each other.

18. The display device of claim 1 , wherein
the first demux circuit area includes a first demux circuit to which a first data signal is applied through a first data input line, and
the second demux circuit area includes a second demux circuit to which a second data signal is applied through a second data input line.

19. The display device of claim 18 , wherein the first data input line and the second data input line are disposed in a same layer as each other.

20. The display device of claim 18 , wherein the first data input line and the second data input line are disposed in different layers from each other.

21. The display device of claim 18 , further comprising:
a first data output line and a second data output line, which are connected to the first demux circuit; and
a third data output line and a fourth data output line, which are connected to the second demux circuit.

22. The display device of claim 21 , wherein the first to fourth data output lines are disposed in a same layer as each other.

23. The display device of claim 21 , wherein at least one selected from the first to fourth data output lines is disposed in a different layer from another selected therefrom.

24. The display device of claim 1 , wherein
the first voltage line includes a first part disposed between the first demux circuit area and the second demux circuit area, and a second part connected to the first part, and
a width of the first part is narrower than a width of the second part.

Assignees

• Samsung Display Co Ltd

Inventors

• Choi Jae-Ho
• Kwak Minchae
• Kim Kyeonghwa
• Kim Mihae
• Oh Kyonghwan
• Jang Sumi
• Jo Seunghan

Classifications

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• H10K59/128

  comprising two independent displays, e.g. for emitting information from two major sides of the display · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• G09F9/30

  in which the desired character or characters are formed by combining individual elements (panels comprising a number of electrodes in a single cell controlling light arriving from an independent light source, e.g. electro-optical or magneto-optical cell, G02F1/00) · CPC title

• G09G3/3291

  in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements · CPC title