Array substrate and display apparatus

Patent metadata

Field	Value
Publication number	US-12167648-B2
Application number	US-202017311606-A
Country	US
Kind code	B2
Filing date	Nov 17, 2020
Priority date	Mar 25, 2020
Publication date	Dec 10, 2024
Grant date	Dec 10, 2024

Abstract

An array substrate is provided. The array substrate includes a gate line extending along a first direction. The gate line includes a plurality of wide portions and a plurality of narrow portions respectively arranged along the first direction, the plurality of wide portions having a first dimension greater than a second dimension of the plurality of narrow portions along a second direction, the second direction at an angle in a range of 80 degrees to 100 degrees with respect to the first direction. An orthographic projection of a respective one of the plurality of wide portions in the respective subpixel on the base substrate overlaps with an orthographic projection of a portion of the semiconductor material layer in the respective subpixel on the base substrate, forming an active layer of the data-write transistor in the respective subpixel.

First claim

What is claimed is:

1. An array substrate, comprising:
a base substrate;
a semiconductor material layer on the base substrate;
a gate line extending along a first direction;
a plurality of pixel driving circuits respectively in a plurality of subpixels configured to respectively drive a plurality of light emitting elements;
wherein a respective one of the plurality of pixel driving circuits comprises a driving transistor configured to generate a driving current for driving a light emitting element to emit light, a data-write transistor configured to write a voltage into a source electrode of the driving transistor, and a compensating transistor;
the gate line comprises a plurality of wide portions and a plurality of narrow portions respectively arranged along the first direction, the plurality of wide portions having a first dimension greater than a second dimension of the plurality of narrow portions along a second direction, the second direction being at an angle in a range of 80 degrees to 100 degrees with respect to the first direction;
an orthographic projection of a respective one of the plurality of wide portions in the respective subpixel on the base substrate overlaps with an orthographic projection of a portion of the semiconductor material layer in the respective subpixel on the base substrate, forming an active layer of the data-write transistor in the respective subpixel; and
a ratio of a channel length to a channel width of the active layer of the data-write transistor is in a range of 1.5:1 to 3:1;
wherein the array substrate further comprises a node connecting line connecting the gate electrode of the driving transistor and one of a source electrode and drain electrode of the compensating transistor;
wherein the plurality of subpixels comprises a first subpixel configured to emit a light of a first color; a second subpixel configured to emit a light of a second color; a third subpixel configured to emit a light of a third color;
orthographic projections of first nodes respectively in the first subpixel, the second subpixel, and the third subpixel on the base substrate are respectively at least 50% covered by orthographic projections of a first anode of a first light emitting element in the first subpixel, a second anode of a second light emitting element in the second subpixel, and a third anode of a third light emitting element in the third subpixel on the base substrate, a respective first node in a respective subpixel comprising a respective gate electrode of the driving transistor and a respective node connecting line in the respective subpixel; and
orthographic projections of node connecting lines respectively in the first subpixel, the second subpixel, and the third subpixel on the base substrate are respectively at least 80% covered by orthographic projections of the first anode of the first light emitting element in the first subpixel, the second anode of the second light emitting element in the second subpixel, and the third anode of the third light emitting element in the third subpixel on the base substrate.

2. The array substrate of claim 1 , wherein the ratio of the channel length to the channel width of the active layer of the data-write transistor is in a range of 2:1 to 3:1.

3. The array substrate of claim 1 , wherein the plurality of wide portions and the plurality of narrow portions are arranged alternately along the first direction; and
the plurality of wide portions are respectively in subpixels along the first direction.

4. The array substrate of claim 1 , wherein the plurality of wide portions has a first line width along the second direction;
the plurality of narrow portions has a second line width along the second direction; and
a ratio of the first line width to the second line width is in a range of 1.1:1 to 3:1.

5. The array substrate of claim 1 , wherein the respective one of the plurality of wide portions has the first dimension greater than the second dimension by protruding towards both sides along the second direction relative to the respective one of the plurality of narrow portions.

6. The array substrate of claim 1 , wherein the respective one of the plurality of pixel driving circuits further comprises a storage capacitor comprising a first capacitor electrode, a second capacitor electrode, and an insulating layer between the first capacitor electrode and the second capacitor electrode;
the second capacitor electrode comprises a main portion and a connection portion connecting main portions of second capacitor electrodes respectively from two adjacent subpixels along the first direction;
the main portion has a wider portion and a narrower portion, the wider portion having a width along a second direction greater than a width of the narrower portion along the direction perpendicular to the first direction; and
orthographic projections of a respective one of the plurality of wide portions and the narrower portion on a plane containing a line arranged along a first direction at least partially overlap with each other.

7. The array substrate of claim 1 , wherein the respective one of the plurality of pixel driving circuits further comprises a storage capacitor comprising a first capacitor electrode, a second capacitor electrode, and an insulating layer between the first capacitor electrode and the second capacitor electrode;
the second capacitor electrode comprises a main portion and a connection portion connecting main portions of second capacitor electrodes respectively from two adjacent subpixels along the first direction; and
orthographic projections of a respective one of the plurality of wide portions and the connection portion on a plane containing a line arranged along a first direction at least partially overlap with each other.

8. The array substrate of claim 1 , further comprising a data line extending along the second direction;
a respective column of pixel driving circuits corresponds to the data line;
the data line comprises a main data line portion and a protruding data line portion;
the protruding data line portion has a dimension along the first direction greater than a dimension of the main data line portion along the first direction;
wherein the orthographic projection of the respective one of the plurality of wide portions on the base substrate partially overlaps with an orthographic projection of the data line on the base substrate forming an overlapped part, a ratio of a dimension of the overlapped part along the first direction to a dimension of the main data line portion along the first direction is in a range of 10% to 100%.

9. The array substrate of claim 1 , further comprising a data line extending along the second direction;
a respective column of pixel driving circuits corresponds to the data line;
the data line comprises a main data line portion and a protruding data line portion;
the protruding data line portion has a dimension along the first direction greater than a dimension of the main data line portion along the first direction;
wherein the orthographic projection of any one of the plurality of wide portions on the base substrate and an orthographic projection of the data line on the base substrate are spaced apart from each other.

10. A display apparatus, comprising the array substrate of claim 1 .

11. An array substrate, comprising a plurality of pixel driving circuits respectively in a plurality of subpixels configured to respectively drive a plurality of light emitting elements;
wherein a respective one of the plurality of pixel driving circuits comprises a driving transistor and a compensating transistor;
wherein the array substrate comprises:
a node connecting line, the node

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Yang Huijuan
• Jiang Xiaofeng
• Shang Tinghua
• Zhou Yang
• Zhang Yi
• Yang Lulu
• Bai Lu

Classifications

• H10K59/80515

  characterised by their shape · CPC title

• H10K59/122

  Pixel-defining structures or layers, e.g. banks · CPC title

• H10K59/1216

  the pixel elements being capacitors · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• H10K50/813

  characterised by their shape · CPC title