Methods and circuits for slew-rate calibration

Patent metadata

Field	Value
Publication number	US-12166485-B2
Application number	US-202217898800-A
Country	US
Kind code	B2
Filing date	Aug 30, 2022
Priority date	Sep 13, 2021
Publication date	Dec 10, 2024
Grant date	Dec 10, 2024

Abstract

Described is an integrated circuit with a driving amplifier that transmits a signal over a link (e.g. a wire) by raising and lowering a voltage on the link. A reference oscillator provides an error measure for the rate at which the voltage transitions between voltages, the slew rate. Slew-rate calibration circuitry adjusts the driving amplifier responsive to the error measure.

First claim

What is claimed is:

1. An integrated circuit (IC) comprising:
an input node to receive an input signal having input-signal transitions;
a multiphase generator coupled to the input node to receive the input-signal, the multiphase generator to issue instances of the input signal, including a first instance of the input signal of a phase offset from a second instance of the input signal;
an oscillator to issue a clock signal of a clock frequency proportional to the phase offset;
calibration circuitry having a calibration input coupled to the oscillator to receive the clock signal and a calibration output coupled to the multiphase generator, the calibration circuitry to adjust the phase offset between the first instance of the input signal and the second instance of the input signal responsive to the clock frequency; and
a driving amplifier having amplifier input nodes coupled to the multiphase generator to receive the instances of the input signal, the driving amplifier to transmit an output signal having output-signal transitions.

2. The IC of claim 1 , wherein the input signal and the output signal have symbol rates independent of the clock frequency.

3. The IC of claim 1 , further comprising a replica of the driving amplifier calibrated responsive to a driver-calibration code, the calibration circuitry having a second calibration input coupled to the replica to receive the driver-calibration code, the calibration circuitry to adjust the phase offset responsive to the clock frequency and the driver-calibration code.

4. The IC of claim 1 , the driving amplifier comprising enabled and disabled driving-amplifier slices, the calibration circuit having a second calibration input to detect a number of the enabled driving-amplifier slices, the calibration circuit to adjust the phase offset responsive to the clock signal and the number of the enabled driving-amplifier slices.

5. The IC of claim 4 , wherein the input signal is periodic.

6. The IC of claim 4 , further comprising:
a second multiphase generator coupled to the input node to receive the input-signal, the second multiphase generator to issue second instances of the input signal, including a third instance of the input signal of a second phase offset from a fourth instance of the input signal;
a second oscillator to issue a second clock signal of a second clock frequency proportional to the second phase offset; and
the calibration circuitry having a second calibration input coupled to the second oscillator to receive the second clock signal and a second calibration output coupled to the second multiphase generator, the calibration circuitry to adjust the second phase offset between the third instance of the input signal and the fourth instance of the input signal responsive to the second clock frequency.

7. The IC of claim 6 , further comprising:
a first driving amplifier having first amplifier input nodes coupled to the multiphase generator to receive the instances of the input signal, the driving amplifier to transmit an output signal having output-signal transitions; and
a second driving amplifier having second amplifier input nodes coupled to the second multiphase generator to receive the second instances of the input signal, the driving amplifier to transmit a second output signal having second output-signal transitions;
wherein the output signal and the second output signal are complementary.

8. The IC of claim 6 , the multiphase generator receiving a first pair of supply voltages and the second multiphase generator receiving a second pair of supply voltage different from the first pair of supply voltages.

9. A method for calibrating a slew rate of an output signal from an amplifier on an integrated circuit, the method comprising:
passing an input signal through a first delay element to produce a first phase-delayed input signal and a second delay element to produce a second phase-delayed input signal;
providing the first phase-delayed input signal and the second phase-delayed input signal to the amplifier, the amplifier to amplify the first phase-delayed input signal and the second phase-delayed input signal on the same output node to produce the output signal, wherein the slew rate of the output signal is a function of a delay between the first phase-delayed input signal and the second phase-delayed input signal;
measuring a frequency of a signal passing through a replica delay element exhibiting a replica delay proportional to the first delay; and
adjusting the delay between the first phase-delayed input signal and the second phase-delayed input signal responsive to the frequency.

10. The method of claim 9 , wherein the slew rate is a rising-edge slew rate for rising transitions of the output signal, the method further comprising:
passing the input signal through a third delay element to produce a third phase-delayed input signal and a fourth delay element to produce a fourth phase-delayed input signal;
providing the third phase-delayed input signal and the fourth phase-delayed input signal to the amplifier, the amplifier to amplify the third phase-delayed input signal and the fourth phase-delayed input signal on the same output node to produce the output signal, wherein a falling-edge slew rate of the output signal is a second function of a second delay between the third phase-delayed input signal and the fourth phase-delayed input signal;
measuring a second frequency of a second signal passing through a second replica delay element exhibiting a second replica delay proportional to the second delay; and
adjusting the second delay between the third phase-delayed input signal and the fourth phase-delayed input signal responsive to the second frequency.

11. The method of claim 9 , wherein the first phase-delayed input signal and the second phase-delayed input signal are two of N phase-delayed input signals, and wherein N is at least three.

12. The method of claim 9 , wherein the amplifier exhibits a driver impedance, the method further comprising:
deriving calibration signals for the driver impedance; and
adjusting the delay between the first phase-delayed input signal and the second phase-delayed input signal responsive to the calibration signals.

13. The method of claim 9 , wherein the amplifier exhibits a drive power, the method further comprising:
storing a power setting for the drive power; and
adjusting the delay between the first phase-delayed input signal and the second phase-delayed input signal responsive to the power setting.

14. The method of claim 9 , further comprising instantiating the replica delay element on the integrated circuit.

15. The method of claim 9 , further comprising disabling the replica delay element on the integrated circuit after the adjusting.

16. An integrated circuit (IC) comprising:
an input node to receive an input signal having input-signal transitions;
means for generating instances of the input signal, including a first instance of the input signal of a phase offset from a second instance of the input signal;
means for generating a clock signal of a clock frequency proportional to the phase offset;
means for adjusting the phase offset between the first instance of the input signal and the second instance of the input signal responsive to the clock frequency; and
a driving amplifier having amplifier input nodes coupled to the means for generating instances of the input signal, the driving amplifier to transmit an output signal having output-signal transitions responsive to the instances of the input signal.

17. The IC of claim 16 , wherein the input

Assignees

• Rambus Inc

Inventors

• Iorga Cosmin

Classifications

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• H03L7/0991

  the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814) · CPC title

• H03L7/195

  in which the counter of the loop counts between two different non zero numbers, e.g. for generating an offset frequency (H03L7/193 takes precedence) · CPC title

• H03L7/0818

  the controlled phase shifter comprising coarse and fine delay or phase-shifting means · CPC title

• H03K19/17784

  for supply voltage · CPC title