LDMOS transistor and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-12166091-B2
Application number	US-202217568856-A
Country	US
Kind code	B2
Filing date	Jan 5, 2022
Priority date	May 29, 2018
Publication date	Dec 10, 2024
Grant date	Dec 10, 2024

Abstract

An LDMOS transistor can include: a field oxide layer structure adjacent to a drain region; and at least one drain oxide layer structure adjacent to the field oxide layer structure along a lateral direction, where a thickness of the drain oxide layer structure is less than a thickness of the field oxide layer, and at least one of a length of the field oxide layer structure and a length of the drain oxide layer structure is adjusted to improve a breakdown voltage performance of the LDMOS transistor.

First claim

What is claimed is:

1. A method of manufacturing a laterally diffused metal oxide semiconductor (LDMOS) transistor, the method comprising:
a) forming a field oxide layer structure adjacent to a drain region on an upper surface of a base layer;
b) forming at least one drain oxide layer structure adjacent to the field oxide layer structure along a lateral direction on the upper surface of the base layer, wherein each of the at least one drain oxide layer structure and the field oxide layer structure comprises an oxide;
c) after forming the at least one drain oxide layer structure, forming a composite drift region comprising a first drift region to an nth drift region, wherein n is a positive integer of at least two, wherein a junction depth of the composite drift region gradually decreases in a direction from the drain region to a channel region, and wherein the field oxide layer extends from the first drift region to a second drift region of the composite drift region; and
d) wherein a thickness of the drain oxide layer structure is less than a thickness of the field oxide layer, and wherein adjustments of at least one of a length of the field oxide layer structure and a length of the drain oxide layer structure change a breakdown voltage performance of the LDMOS transistor.

2. The method according to claim 1 , wherein the composite drift region has a second doping type in the drain region of the base layer, wherein the junction depth of the composite drift region gradually decreases in the direction from the drain region to the channel region to improve an on-resistance performance of the LDMOS transistor.

3. The method according to claim 2 , further comprising forming a composite well region having a first doping type in a source region of the base layer, wherein the composite well region close to the drain region comprises a first convex region in the lateral direction, and the composite well region toward the bottom of the base layer comprises a second convex region in a vertical direction.

4. The method according to claim 2 , wherein a doping concentration of the composite drift region gradually decreases in the direction from the drain region to the channel region.

5. The method according to claim 3 , wherein after the forming the field oxide layer structure, and before the forming at least one drain oxide layer structure, further comprising:
a) forming a first well region; and
b) forming a second well region after forming the composite drift region,
c) wherein a width of the second well region is greater than a width of the first well region, a depth of the first well region is greater than a depth of the second well region, and the composite well region is formed by superposing the first well region and the second well region.

6. The method according to claim 5 , wherein a doping concentration of the first well region is less than a doping concentration of the second well region.

7. The method according to claim 5 , wherein when the number of the drain oxide layer structures is greater than 1 , a thickness of the drain oxide layer structures gradually decreases in the direction from the drain region to the channel region.

8. The method according to claim 7 , before the forming the second well region, further comprising:
a) forming a gate dielectric layer; and
b) forming a gate conductor on the gate dielectric layer and a portion of the drain oxide layer structure, c) wherein the gate dielectric layer is adjacent to the drain oxide layer structure, and the gate conductor fully covers a thinnest drain oxide layer structure and at least partially covers the drain oxide layer structure adjacent to the thinnest drain oxide layer structure.

9. The method according to claim 1 , further comprising:
a) forming a drain region with a second doping type in the base layer; and
b) forming a source region with the second doping type and a body region with the first doping type in the base layer.

10. The method according to claim 1 , wherein each of the at least one drain oxide layer structure and the field oxide layer structure is centered about the upper surface of the base layer.

Assignees

• Silergy Semiconductor Technology Hangzhou Ltd

Inventors

• Wang Meng
• Yu Hui

Classifications

• H10W10/13

  formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI] · CPC title

• H10W10/012

  using local oxidation of silicon [LOCOS] · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D30/0281

  of lateral DMOS [LDMOS] FETs · CPC title

• H10D30/65 Primary

  Lateral DMOS [LDMOS] FETs · CPC title