Processing of data by multiple graphic processing devices

Patent metadata

Field	Value
Publication number	US-12164922-B2
Application number	US-202017131633-A
Country	US
Kind code	B2
Filing date	Dec 22, 2020
Priority date	Dec 22, 2020
Publication date	Dec 10, 2024
Grant date	Dec 10, 2024

Abstract

Examples described herein relate to a system that after decoding of video by the first device, provides a memory address of decoded video in the memory device to a second driver for a second device and perform a second device driver that causes the second device to access the decoded video directly from a translation of the memory address of the memory device, wherein the second device is to access the decoded video with memory properties of the decoded video and decompression information of the decoded video. In some examples, the first device comprises one or more of: a graphics processing unit integrated with a central processing unit (CPU), a discrete graphics processing unit, or a video decoder accelerator. In some examples, the second device comprises one or more of: a graphics processing unit integrated with a central processing unit (CPU) or a discrete graphics processing unit. In some examples, the memory properties of the decoded video comprise swizzle information. In some examples, decompression information of the decoded video comprise a decompression scheme or decompression key.

First claim

What is claimed is:

1. A method comprising:
receiving a request to perform video decoding and video processing at a first graphics driver for a first graphics processing device, wherein the first graphics processing device comprises an integrated graphics processing unit (GPU);
after decoding of the video: the first graphics driver providing a memory address of the decoded video to a second graphics driver for a second graphics processing device and the first graphics processing device storing memory properties associated with the decoded video into memory, wherein the second graphics processing device comprises a discrete GPU; and
the second graphics driver causing the second graphics processing device to access the decoded video directly from a translation of the memory address of a memory device, wherein the second graphics processing device is to access the decoded video with the memory properties of the decoded video and decompression information of the decoded video and perform the video processing on decoded video, wherein:
the video processing comprises one or more of: resolution adjustment of video frames, color modification, or segmentation,
the memory properties of the decoded video comprise swizzle information, and
the swizzle information defines an association between memory addresses and positions in an array.

2. The method of claim 1 , wherein the first graphics driver is associated with the first graphics processing unit device that is integrated with a central processing unit (CPU).

3. The method of claim 1 , wherein the second graphics driver is associated with the second graphics processing device unit integrated with a central processing unit (CPU).

4. The method of claim 1 , wherein the decompression information of the decoded video comprise a decompression scheme or decompression key.

5. The method of claim 1 , comprising:
providing a memory address conversion for the second graphics driver to convert the memory address into a physical address for the second graphics processing device to access the decoded video.

6. The method of claim 1 , wherein the decoded video is in NV12 format.

7. The method of claim 1 , comprising:
providing a second memory address of the processed decoded video to an issuer of the request.

8. The method of claim 7 , wherein the processed video is in RGB format.

9. At least one non-transitory computer-readable medium, comprising instructions stored thereon, that if executed by at least one processor, is to cause the at least one processor to:
perform a first device driver, that after decoding of video, provides a memory address of the decoded video to a second device driver for a second graphics processing device and
perform the second device driver that causes the second graphics processing device to access the decoded video directly from a translation of the memory address of a memory device and access memory properties of the decoded video, wherein:
a first graphics processing device, associated with the first device driver, performs the decoding of the video and stores the memory properties of the decoded video,
the second graphics processing device is to access the decoded video with the memory properties of the decoded video and decompression information of the decoded video,
the second graphics processing device is to perform video processing on the decoded video,
the first graphics processing device comprises a video decoder accelerator,
the second graphics processing device comprises a discrete graphics processing unit (GPU),
the memory properties of the decoded video comprise swizzle information, and
the swizzle information defines an association between memory addresses and positions in an array.

10. The computer-readable medium of claim 9 , wherein the second device driver is associated with a graphics processing unit integrated with a central processing unit (CPU) or the discrete graphics processing unit.

11. The computer-readable medium of claim 9 , wherein the decompression information of the decoded video comprise a decompression scheme or decompression key.

12. A system comprising:
a memory device;
a first device coupled to the memory device;
a second device coupled to the memory device; and
a central processing unit (CPU), the CPU to:
perform a first device driver, that after decoding of video by the first device, provides a memory address of decoded video in the memory device to a second device driver for a second device and
perform the second device driver that causes the second device to access the decoded video directly from a translation of the memory address of the memory device, wherein the second device is to access the decoded video with memory properties of the decoded video and decompression information of the decoded video, wherein:
the first device is to store the memory properties of the decoded video into the memory device,
the second device is to perform video processing on the decoded video,
the memory properties of the decoded video comprise swizzle information, and
the swizzle information is to define an association between memory addresses and positions in an array.

13. The system of claim 12 , wherein the first device comprises one or more of: a graphics processing unit integrated with a central processing unit (CPU), a discrete graphics processing unit, or a video decoder accelerator.

14. The system of claim 12 , wherein the second device comprises one or more of: a graphics processing unit integrated with a central processing unit (CPU) or a discrete graphics processing unit.

15. The system of claim 12 , wherein the decompression information of the decoded video comprise a decompression scheme or decompression key.

16. The system of claim 12 , wherein the translation of the memory address comprises a conversion of the memory address to a physical address.

Assignees

• Intel Corp

Inventors

• Kumar Gaurav
• Wang Changliang L
• Dai Haichun
• Ye Hongbin
• Silvas Ronald W

Classifications

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/3888

  controlled by a single instruction for multiple threads [SIMT] in parallel · CPC title

• G06T1/60 Primary

  Memory management · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• H04N19/59

  involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution · CPC title