Tininess detection

Patent metadata

Field	Value
Publication number	US-12164881-B2
Application number	US-202117384001-A
Country	US
Kind code	B2
Filing date	Jul 23, 2021
Priority date	Jul 23, 2021
Publication date	Dec 10, 2024
Grant date	Dec 10, 2024

Abstract

An apparatus comprises floating-point processing circuitry to perform a floating-point operation with rounding to generate a floating-point result value; and tininess detection circuitry to detect a tininess status indicating whether an outcome of the floating-point operation is tiny. A tiny outcome corresponds to a non-zero number with a magnitude smaller than a minimum non-zero magnitude representable as a normal floating-point number in a floating-point format to be used for the floating-point result value. The tininess detection circuitry comprises hardware circuit logic configured to support both before rounding tininess detection and after rounding tininess detection for detecting the tininess status.

First claim

The invention claimed is:

1. An apparatus comprising:
floating-point processing circuitry to perform a floating-point operation with rounding to generate a floating-point result value; and
tininess detection circuitry to detect a tininess status indicating whether an outcome of the floating-point operation with rounding is tiny, where a tiny outcome corresponds to a non-zero number with a magnitude smaller than a minimum non-zero magnitude representable as a normal floating-point number in a floating-point format to be used for the floating-point result value;
the tininess detection circuitry comprising hardware circuit logic configured to support both before rounding tininess detection and after rounding tininess detection for detecting the tininess status;
in which the tininess detection circuitry is configured to select, based on a software-programmable control parameter, whether to detect the tininess status according to the before rounding tininess detection or the after rounding tininess detection.

2. The apparatus according to claim 1 , in which the tininess detection circuitry comprises a shared datapath used for both the before rounding tininess detection and the after rounding tininess detection.

3. The apparatus according to claim 2 , in which the tininess detection circuitry comprises selection circuitry to select, based on whether the tininess detection circuitry is to perform the before rounding tininess detection or the after rounding tininess detection, an intermediate value, other than the tininess status itself, for use in determining the tininess status.

4. The apparatus according to claim 1 , in which the floating-point processing circuitry is configured to perform injection rounding to generate an injection-rounded significand for the floating-point result value; and
the tininess detection circuitry is configured to detect the tininess status based on the injection-rounded significand, for both the before rounding tininess detection and the after rounding tininess detection.

5. The apparatus according to claim 1 , in which the floating-point processing circuitry is configured to generate an unrounded significand;
the floating-point processing circuitry comprises non-injection rounding circuitry to round the unrounded significand to generate a rounded result significand for the floating-point result value; and
the tininess detection circuitry is configured to detect the tininess status based on the unrounded significand, for both the before rounding tininess detection and the after rounding tininess detection.

6. The apparatus according to claim 1 , in which the floating-point processing circuitry is configured to perform the rounding by selectively performing a rounding addition to generate a rounded result significand for the floating-point result value; and
the tininess detection circuitry is configured to perform the after rounding tininess detection without performing any further rounding addition other than the rounding addition performed by the floating-point processing circuitry to generate the rounded result significand for the floating-point result value.

7. The apparatus according to claim 1 , in which in the floating-point operation with rounding, the floating-point processing circuitry is configured to generate a result exponent, and a significand;
the apparatus comprises shifting circuitry to perform a shift on the significand by a variable number of bits, to generate a shifted significand; and
the tininess detection circuitry is configured to detect the tininess status based on the shifted significand generated by the shifting circuitry, for both the before rounding tininess detection and the after rounding tininess detection.

8. The apparatus according to claim 7 , in which:
the apparatus comprises shift control circuitry to select the variable number of bits for the shift;
when the result exponent is less than a minimum exponent supported by the floating-point format for non-zero normal floating-point numbers, the shift is a right shift by Emin-E bits, where Emin is the minimum exponent and E is the result exponent;
when the result exponent is greater than or equal to the minimum exponent and the most significant bit of the significand is one, the variable number of bits is zero; and
when the result exponent is greater than or equal to the minimum exponent and the most significant bit of the significand is zero, the shift is a left shift by a number of bits corresponding to a minimum of lzc and (E-Emin), where lzc is a number of leading zeroes in the significand.

9. The apparatus according to claim 7 , in which the tininess detection circuitry comprises range identifying circuitry to identify whether a result magnitude represented by the result exponent and the significand is within a predetermined range for which the before rounding tininess detection and the after rounding tininess detection are capable of providing different outcomes for the tininess status for at least one rounding mode.

10. The apparatus according to claim 9 , in which the range identifying circuitry is configured to identify, based on the shifted significand, whether the result magnitude is within the predetermined range.

11. The apparatus according to claim 9 , in which:
when the result magnitude is determined by the range identifying circuitry to be within the predetermined range, at least for the after rounding tininess detection and for at least one rounding mode, the tininess detection circuitry is configured to set the tininess status based on one or more lower bits of the shifted significand which are at bit positions which would be discarded if the shifted significand was truncated to fit within the floating-point format to be used for the floating-point result; and
when the result magnitude is determined by the range identifying circuitry to be outside the predetermined range, the tininess detection circuitry is configured to set the tininess status independent of said one or more lower bits of the shifted significand.

12. The apparatus according to claim 9 , in which:
when the result magnitude is determined by the range identifying circuitry to be greater the predetermined range, for both the before rounding tininess detection and the after rounding tininess detection, the tininess detection circuitry is configured to set the tininess status to indicate that the outcome of the floating-point operation with rounding is not tiny;
when the result magnitude is determined by the range identifying circuitry to be smaller than the predetermined range, for both the before rounding tininess detection and the after rounding tininess detection, the tininess detection circuitry is configured to set the tininess status to indicate that the outcome of the floating-point operation with rounding is tiny.

13. The apparatus according to claim 12 , in which the floating-point processing circuitry is configured to generate the unrounded significand; and
the range identifying circuitry is configured to determine that the result magnitude is within the predetermined range when the result magnitude X satisfies the bounds 2 Emin >x ≥2 Emin -ulp/2, where ulp is a minimum positive non-zero number representable as a subnormal number in the floating-point format to be used for the floating-point result value.

14. The apparatus according to claim 9 , in which the floating-point processing circuitry is configured to generate the unrounded significand; and
when the result magnitude is determined by the range identifying circuitry to be within the predetermined range, for the before rounding tininess detection, the tininess detectio

Assignees

• Advanced Risc Mach Ltd

Inventors

• Lutz David Raymond
• Russinoff David M
• Valsaraju Harsha

Classifications

• G06F7/49947

  Rounding · CPC title

• G06F7/10

  Selecting, i.e. obtaining data of one kind from those record carriers which are identifiable by data of a second kind from a mass of ordered or randomly- distributed record carriers · CPC title

• G06F5/012

  in floating-point computations · CPC title

• G06F7/483 Primary

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title

• G06F7/49915 Primary

  Mantissa overflow or underflow in handling floating-point numbers · CPC title