Display panel and display apparatus

US12164716B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12164716-B2
Application numberUS-202117789188-A
CountryUS
Kind codeB2
Filing dateAug 16, 2021
Priority dateSep 16, 2020
Publication dateDec 10, 2024
Grant dateDec 10, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Embodiments of the present disclosure provide a display panel, including a display substrate (1); and a touch electrode (2) and a shielding electrode (6) arranged on the display substrate (1); where the shielding electrode (6) and the touch electrode (2) are sequentially arranged in a direction away from the display substrate (1); and an orthographic projection of the shielding electrode (6) on the display substrate (1) at least partially overlaps an orthographic projection of the touch electrode (2) on the display substrate (1), the shielding electrode comprises shielding units arranged in an array, in a row direction of the array, M shielding units each having a load value x are provided, M*x≤P; and in a column direction of the array, N shielding units each having a load value y are provided, N*y≤P; P is a maximum load capacity of a driver chip for providing signals for the shielding electrode.

First claim

Opening claim text (preview).

What is claimed is: 1. A display panel, comprising a display substrate; and a touch electrode and a shielding electrode arranged on the display substrate; wherein the shielding electrode and the touch electrode are sequentially arranged in a direction away from the display substrate; and an orthographic projection of the shielding electrode on the display substrate at least partially overlaps an orthographic projection of the touch electrode on the display substrate, wherein the shielding electrode comprises a plurality of shielding units spaced apart from each other, the plurality of shielding units are arranged in an array, wherein in a row direction of the array of shielding units, M shielding units are provided, each of the shielding units has a load value x, and M*x≤P; and in a column direction of the array of shielding units, N shielding units are provided, each of the shielding units has a load value y, and N*y≤P; where P is a maximum load capacity of a driver chip for providing signals for the shielding electrode. 2. The display panel according to claim 1 , wherein the touch electrode comprises a plurality of touch units arranged in an array; and in a row and/or column direction of the array of touch units, the shielding units correspond to the touch units in a one to one manner or in a one to many manner. 3. The display panel according to claim 2 , wherein, in a row direction of the array of touch units, A touch units are provided, each of the touch units has a load value a, and A*a≤P; and in a column direction of the array of touch units, B touch units are provided, each of the touch units has a load value b, and B*b≤P; where P is a maximum load capacity of a touch driver chip for providing signals for the touch electrode. 4. The display panel according to claim 1 , further comprising shielding signal lines arranged in the same layer as the shielding electrode; wherein each of the shielding units is individually connected to one of the shielding signal lines, and the shielding signal lines connected to one or more rows of shielding units are connected together to be connected into the driver chip. 5. The display panel according to claim 4 , wherein the shielding signal lines comprise a first signal line and second signal lines, the first signal line surrounds a periphery of the array of shielding units, a part of the second signal lines are distributed at the periphery of the array of shielding units, and another part of the second signal lines are distributed in spaces between rows of the array of shielding units; and the second signal lines are respectively and independently connected to the shielding units, and connected to the first signal line, and the first signal line is connected to the driver chip. 6. The display panel according to claim 4 , wherein the display substrate comprises a plurality of sub-pixels arranged in an array; and the shielding units are in a grid shape, and an orthographic projection of the shielding units on the display substrate does not overlap the sub-pixels; and an orthographic projection of the shielding signal lines on the display substrate does not overlap the sub-pixels. 7. The display panel according to claim 6 , wherein the touch units are in a grid shape, and an orthographic projection of the touch units on the display substrate does not overlap the sub-pixels; and a grid density of the shielding units is smaller than or equal to a grid density of the touch units; and a grid density of the touch units is smaller than a distribution density of the sub-pixels. 8. The display panel according to claim 7 , further comprising touch signal lines on a side of the shielding electrode away from the display substrate, and on a side of the touch electrode close to the display substrate; wherein each of the touch units is individually connected to one of the touch signal lines; and an orthographic projection of the touch signal lines on the display substrate overlaps an orthographic projection of the touch electrode on the display substrate. 9. The display panel according to claim 8 , further comprising a first insulation layer between the touch signal lines and the touch electrode; wherein at least one first via is opened in the first insulation layer in a region corresponding to each of the touch units, and the touch unit is connected to the touch signal line configured to provide signals for the touch unit through the first via. 10. The display panel according to claim 9 , wherein a plurality of first vias are opened in the first insulation layer in a region corresponding to each of the touch units; wherein the plurality of first vias are uniformly distributed and connected to each other through the touch signal lines. 11. The display panel according to claim 9 , wherein one first via is opened in the first insulation layer in a region corresponding to each of the touch units; wherein for a column of touch units, from top to bottom, first vias corresponding to the touch units are sequentially arranged from an upper right corner of the touch units to a lower left corner of the touch units. 12. The display panel according to claim 7 , further comprising floating electrodes floating and disposed in the same layer as the touch electrode, an orthographic projection of the floating electrodes on the display substrate does not overlap an orthographic projection of the touch electrode on the display substrate. 13. The display panel according to claim 12 , wherein the floating electrodes are in a grid shape, and an orthographic projection of the floating electrodes on the display substrate does not overlap the sub-pixels. 14. The display panel according to claim 13 , wherein the floating electrodes are distributed in a region, where the touch units are located, with a ratio of distribution area less than 40%. 15. The display panel according to claim 1 , wherein the shielding electrode and the touch electrode are configured to input a same signal during touching. 16. A display apparatus, comprising the display panel according to claim 1 . 17. A display panel, comprising a display substrate; and a touch electrode and a shielding electrode arranged on the display substrate; wherein the shielding electrode and the touch electrode are sequentially arranged in a direction away from the display substrate; and an orthographic projection of the shielding electrode on the display substrate at least partially overlaps an orthographic projection of the touch electrode on the display substrate, wherein the shielding electrode and the touch electrode are configured to input a same signal during touching. 18. A display panel, comprising a display substrate; and a touch electrode and a shielding electrode arranged on the display substrate; wherein the shielding electrode and the touch electrode are sequentially arranged in a direction away from the display substrate; and an orthographic projection of the shielding electrode on the display substrate at least partially overlaps an orthographic projection of the touch electrode on the display substrate, wherein the touch electrode comprises a plurality of touch units arranged in an array, and wherein in a row direction of the array of touch units, A touch units are provided, each of the touch units has a load value a, and A*a≤P; and in a column direction of the array of touch units, B touch units are provided, each of the touch units has a load value b, and B*b≤P; where P is a maximum load capacity of a touch driver chip for providing signals for the touch elect

Assignees

Inventors

Classifications

  • G06F3/0412Primary

    Digitisers structurally integrated in a display · CPC title

  • G06F3/0446Primary

    using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes · CPC title

  • OLEDs integrated with touch screens · CPC title

  • Shielding, e.g. light-blocking means over the TFTs · CPC title

  • Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads · CPC title

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What does patent US12164716B2 cover?
Embodiments of the present disclosure provide a display panel, including a display substrate (1); and a touch electrode (2) and a shielding electrode (6) arranged on the display substrate (1); where the shielding electrode (6) and the touch electrode (2) are sequentially arranged in a direction away from the display substrate (1); and an orthographic projection of the shielding electrode (6) on…
Who is the assignee on this patent?
Chengdu Boe Optoelect Tech Co, Boe Technology Group Co Ltd, Beijing Boe Technology Dev Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F3/0412. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 10 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).