Eyewear with a system on a chip with simultaneous USB communications

Patent metadata

Field	Value
Publication number	US-12164449-B2
Application number	US-202117409895-A
Country	US
Kind code	B2
Filing date	Aug 24, 2021
Priority date	Aug 24, 2021
Publication date	Dec 10, 2024
Grant date	Dec 10, 2024

Abstract

Eyewear including a frame having a first side and a second side, a first temple extending from the first side of the frame, a second temple extending from the second side of the frame, electronic components, a first system on a chip (SoC) adjacent the first side of the frame coupled to a first set of the electronic components, and a second system on a chip adjacent the second side, the second SoC coupled to the first SoC and to a second set of the plurality of electronic components. Processing workloads are balanced between the first SoC and the second SoC by performing a first set of operations with the first SoC and performing a second set of operations with the second SoC.

First claim

What is claimed is:

1. Eyewear, comprising:
a frame having a first side and a second side;
a first temple portion adjacent the first side of the frame;
a second temple portion adjacent the second side of the frame;
a plurality of electronic components;
a system on a chip (SoC) disposed within the first temple portion, the SoC comprising a central processing unit (CPU), a graphical processing unit (GPU), an image signal processor (ISP), and a universal serial bus (USB) component including a USB connection interface with a first USB sub connection interface and a second USB sub connection interface, wherein the USB connection interface has a USB 3.0 connection interface pinout, the first USB sub connection interface has a first subset of the USB 3.0 connection interface pinout that only has power, ground, and D+/D− connection pins and supports USB 2.0 communications but not USB 3.0 communications, and the second USB sub connection interface has a second subset of the USB 3.0 connection interface pinout that supports USB 3.0 communications; and
another SoC disposed within the second temple portion, the other SoC comprising another CPU, another GPU, another ISP, and another USB connection interface coupled to the first USB sub connection interface;
wherein the first USB sub connection interface of the USB connection interface of the SoC is coupled to the other USB connection interface of the other SoC and the second USB sub connection interface of the USB connection interface of the SoC is coupled to one of the plurality of electronic components or an external device, wherein the USB connection interface of the USB component is simultaneously connected to the other SoC via the first USB sub connection interface and the one of the plurality of electronic components via the second USB sub connection interface.

2. The eyewear of claim 1 , further comprising at least one externally accessible connector coupled to the second USB sub connection interface.

3. The eyewear of claim 2 , wherein the first USB sub connection interface of the USB component is configured for high speed (HS) USB communications and the second USB sub connection interface of the USB component is configured for SuperSpeed (SS) USB communications.

4. The eyewear of claim 3 , wherein the USB component of the SoC is configured for communication in a host state for HS USB communications via the first USB sub connection interface and in a device state for SS USB communications via the second USB connection interface.

5. The eyewear of claim 1 , wherein the external device is a personal computer.

6. The eyewear of claim 1 , wherein the one of the plurality of electronic components is an additional SoC and the additional SoC is adjacent a second side of the frame.

7. The eyewear of claim 6 , wherein one of the plurality of electronic components includes a USB hub or a modem and the external device is a personal computer.

8. The eyewear of claim 1 , wherein the plurality of electronic components comprises an additional SoC, the other USB connection interface of the other SoC has a third USB sub connection interface coupled to the first USB connection interface of the SoC and a fourth USB sub connection interface coupled to the additional SoC.

9. A method for use with eyewear comprising a frame having a first side and a second side, a first temple portion adjacent the first side of the frame, and a second temple portion adjacent the second side of the frame, the eyewear further comprising a system on a chip (SoC) disposed within the first temple portion comprising a central processing unit (CPU), a graphical processing unit (GPU), an image signal processor (ISP), and a universal serial bus (USB) component including a USB connection interface with a first USB sub connection interface and a second USB sub connection interface, wherein the USB connection interface has a USB 3.0 connection interface pinout, the first USB sub connection interface has a first subset of the USB 3.0 connection interface pinout that only has power, ground, and D+/D− connection pins and supports USB 2.0 communications but not USB 3.0 communications, and the second USB sub connection interface has a second subset of the USB 3.0 connection interface pinout that supports USB 3.0 communications, and another SoC disposed within the second temple portion comprising another CPU, another GPU, another ISP, and another USB connection interface coupled to the first USB sub connection interface of the SoC, the method comprising:
establishing communication with the other SoC in the second temple portion through the first USB sub connection interface of the SoC in the first temple portion;
establishing communication with an electronic component through the second USB sub connection interface; and
communicating with the other SoC in the second temple through the first USB sub connection interface of the SoC in the first temple and communicating with the second component through the second USB sub connection interface of the SoC in the first temple, wherein the USB connection interface of the USB component is simultaneously connected to the other SoC via the first USB sub connection interface and the electronic component via the second USB sub connection interface.

10. The method of claim 9 , further comprising:
configuring the first USB sub connection interface of the USB component for high speed (HS) USB communications; and
configuring the second USB sub connection interface of the USB component for SuperSpeed (SS) USB communications.

11. The method of claim 10 , wherein the configuring the first USB sub connection interface of the USB component for high speed (HS) USB communications includes configuring the USB component of the SoC in a host state for HS USB communications via the first USB sub connection interface; and
wherein the configuring the second USB sub connection interface of the USB component for SuperSpeed (SS) USB communications includes configuring the USB component of the SoC in a device state for SS USB communications via the second USB sub connection interface.

12. The method of claim 9 , wherein at least one peripheral component of an external device is coupled to the second USB sub connection interface.

13. The method of claim 9 , wherein the electronic component includes a USB hub or a modem.

14. The method of claim 9 , wherein the eyewear comprises an additional SoC, the other USB connection interface of the other SoC has a third USB sub connection interface coupled to the first USB connection interface of the SoC and a fourth USB sub connection interface coupled to the additional SoC.

15. A non-transitory computer readable medium having instructions for use with eyewear comprising a frame having a first side and a second side, a first temple portion adjacent the first side of the frame, and a second temple portion adjacent the second side of the frame, the eyewear further comprising a system on a chip (SoC) disposed within the first temple portion comprising a central processing unit (CPU), a graphical processing unit (GPU), an image signal processor (ISP), and a universal serial bus (USB) component including a USB connection interface with a first USB sub connection interface and a second USB sub connection interface, wherein the USB connection interface has a USB 3.0 connection interface pinout, the first USB sub connection interface has a first subset of the USB 3.0 connection interface pinout that only has power, ground, and D+/D− connection pins and supports USB 2.0 communications but not USB 3.0 communications, and the second USB sub connection interface has a second subset of

Assignees

• Vadivelu Praveen Babu
• Heger Jason
• Nilles Gerald
• Feinman Alex
• Hu Dunxu
• Snap Inc

Inventors

• Vadivelu Praveen Babu
• Heger Jason
• Nilles Gerald
• Feinman Alex
• Hu Dunxu

Classifications

• G06F2213/0042

  Universal serial bus [USB] · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G02C11/10

  Electronic devices other than hearing aids · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/20 Primary

  for access to input/output bus · CPC title