Array substrate and manufacturing method thereof, display panel, display device and pixel driving circuit

Patent metadata

Field	Value
Publication number	US-12161035-B2
Application number	US-202318502168-A
Country	US
Kind code	B2
Filing date	Nov 6, 2023
Priority date	Mar 28, 2019
Publication date	Dec 3, 2024
Grant date	Dec 3, 2024

Abstract

Disclosed are an array substrate and a display panel, including: a base substrate; and a wiring layer, an anode layer, and a light-emitting layer which are stacked on the base substrate sequentially, wherein the wiring layer includes a signal wiring, a first wiring and a second wiring, a projection of the first wiring on the base substrate is separated from a projection of the second wiring on the base substrate, the first and second wirings are respectively disposed on two sides of the anode layer below the anode layer, the signal wiring is between the first and second wirings, the projections of the first and second wirings on the base substrate respectively overlap projections of two sides of the anode layer on the base substrate, and a length of the second wiring is less than that of the signal wiring in an extension direction of the signal wiring.

First claim

What is claimed is:

1. An array substrate, comprising:
a base substrate; and
a wiring layer, an anode layer, and a light-emitting layer which are stacked on the base substrate sequentially, wherein the wiring layer comprises a signal wiring, a first wiring, and a second wiring,
wherein a projection of the first wiring on the base substrate is separated from a projection of the second wiring on the base substrate, and the first wiring and the second wiring are respectively disposed on two sides of the anode layer below the anode layer;
wherein the signal wiring is located between the first wiring and the second wiring, and the projection of the first wiring on the base substrate and the projection of the second wiring on the base substrate are respectively overlapped with projections of two sides of the anode layer on the base substrate; and
wherein a length of the second wiring is less than a length of the signal wiring in an extension direction of the signal wiring.

2. The array substrate according to claim 1 , wherein the first wiring and the second wiring are disposed on two sides of a central line of the anode layer.

3. The array substrate according to claim 2 , wherein the extension direction of the signal wiring, an extension direction of the first wiring, and an extension direction of the second wiring are parallel to the central line of the anode layer.

4. The array substrate according to claim 3 , wherein an area of a portion of the projection of the first wiring on the base substrate overlapping with a projection of the anode layer on the base substrate is substantially equal to an area of a portion of the projection of the second wiring on the base substrate overlapping with the projection of the anode layer on the base substrate.

5. The array substrate according to claim 1 , wherein an area of a portion of the projection of the second wiring on the base substrate overlapping with a projection of the anode layer on the base substrate is less than an area of a portion of a projection of the signal wiring on the base substrate overlapping with the projection of the anode layer on the base substrate.

6. The array substrate according to claim 1 , wherein a length of a portion of the projection of the first wiring on the base substrate overlapping with a projection of the anode layer on the base substrate in the extension direction of the signal wiring is equal to a length of a portion of the projection of the second wiring on the base substrate overlapping with the projection of the anode layer on the base substrate in the extension direction of the signal wiring.

7. The array substrate according to claim 6 , wherein the length of the portion of the projection of the second wiring on the base substrate overlapping with the projection of the anode layer on the base substrate in the extension direction of the signal wiring is less than a length of a portion of a projection of the signal wiring on the base substrate overlapping with the projection of the anode layer on the base substrate in the extension direction of the signal wiring.

8. The array substrate according to claim 1 , wherein a pattern, formed by an overlap between the projection of the second wiring on the base substrate and a projection of the anode layer on the base substrate, is in a trapezoidal shape.

9. The array substrate according to claim 8 , wherein in the extension direction of the signal wiring, a length of the pattern on a side of the pattern close to the signal wiring is greater than a length of the pattern on a side of the pattern away from the signal wiring, wherein the pattern is formed by the overlap between the projection of the second wiring on the base substrate and the projection of the anode layer on the base substrate.

10. The array substrate according to claim 1 , wherein a surface of the first wiring facing away from the base substrate is flush with a surface of the second wiring facing away from the base substrate.

11. The array substrate according to claim 1 , wherein the first wiring and the second wiring are located in the same wiring layer.

12. The array substrate according to claim 1 , wherein the second wiring is a source drain (SD) metallic wiring.

13. The array substrate according to claim 1 , wherein the signal wiring, the first wiring, and the second wiring are located in the same wiring layer.

14. The array substrate according to claim 1 , wherein a distance from the anode layer to the base substrate in a region A corresponding to the first wiring is substantially equal to a distance from the anode layer to the base substrate in a region B corresponding to the second wiring.

15. The array substrate according to claim 1 , wherein the signal wiring is configured to receive a data signal.

16. The array substrate according to claim 1 , wherein the second wiring is configured to receive a constant voltage signal.

17. The array substrate according to claim 1 , wherein the first wiring is configured to receive a power supply signal.

18. The array substrate according to claim 1 , wherein the light-emitting layer is a green pixel.

19. A display panel comprising the array substrate according to claim 1 .

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Li Meng
• Du Sen
• Cheng Tianyi
• Zhang Tiaomei
• Huang Yao
• Liu Tingliang

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H10K59/1201

  Manufacture or treatment · CPC title

• G09G3/3258

  with pixel circuitry controlling the voltage across the light-emitting element · CPC title

• H10K2102/351

  Thickness · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title