Amplifier and driver circuit

Patent metadata

Field	Value
Publication number	US-12160205-B2
Application number	US-202018005928-A
Country	US
Kind code	B2
Filing date	Jul 21, 2020
Priority date	Jul 21, 2020
Publication date	Dec 3, 2024
Grant date	Dec 3, 2024

Abstract

An amplifier circuit comprises a variable degeneration circuit connected to emitter terminals of transistors, and a variable negative capacitance circuit connected to differential output signal terminals. The variable degeneration circuit includes a variable capacitor and a resistor. The variable negative capacitance circuit, which is a variable current source, includes a transistor, a capacitor, and a variable current source. The variable negative capacitance circuit includes transistors, a capacitor, and variable current sources.

First claim

The invention claimed is:

1. An amplifier circuit, comprising:
a first transistor and a second transistor having a differential configuration in which base terminals of the first transistor and the second transistor are connected to differential input signal terminals of an amplifier circuit,
a third transistor having a base terminal connected to a collector terminal of the second transistor, a collector terminal connected to a power supply voltage, and an emitter terminal connected to a first output signal terminal on a positive phase side of an amplifier circuit;
a fourth transistor having a base terminal connected to a collector terminal of the first transistor, a collector terminal connected to the power supply voltage, and an emitter terminal connected to a second output signal terminal on an opposite phase side of the amplifier circuit, a variable degeneration circuit connected to emitter terminals of the first transistor and the second transistor; and
a variable negative capacitance circuit connected to the first output signal terminal and second output signal terminal;
wherein the variable negative capacitance circuit includes:
fifth and sixth transistors whose collector terminals are connected to the first output signal terminal and the second output signal terminal and whose base terminals and collector terminals are connected in a cross-coupled manner;
a first variable current source having a first end connected to an emitter terminal of the fifth transistor and a second end connected to ground; and
a second variable current source having a first end connected to an emitter terminal of the sixth transistor and a second end connected to ground.

2. The amplifier circuit according to claim 1 , wherein the variable negative capacitance circuit further includes:
a capacitor connected between an emitter terminal of the fifth transistor and an emitter terminal of the sixth transistor.

3. The amplifier circuit according to claim 2 , wherein the variable degeneration circuit includes:
a variable capacitance and a first resistor connected in parallel between an emitter terminal of the first transistor and an emitter terminal of the second transistor.

4. The amplifier circuit according to claim 1 , wherein the variable negative capacitance circuit further includes:
a third capacitor a fourth capacitor connected in series between an emitter terminal of the fifth transistor and an emitter terminal of the sixth transistor.

5. The amplifier circuit according to claim 4 , wherein the variable degeneration circuit includes:
a first resistor connected between an emitter terminal of the first transistor and an emitter terminal of the second transistor;
a first capacitor and a first variable resistor connected in series between an emitter terminal of the first transistor and an emitter terminal of the second transistor; and
a second variable resistor and a second capacitor connected in series between the emitter terminal of the first transistor and the emitter terminal of the second transistor.

6. The amplifier circuit according to claim 5 , wherein an arrangement of the variable degeneration circuit in a direction from the emitter terminal of the first transistor to the emitter terminal of the second transistor and an arrangement of the variable degeneration circuit in a direction from the emitter terminal of the second transistor to the emitter terminal of the first transistor are matched.

7. The amplified circuit according to claim 6 , wherein an arrangement of the variable negative capacitance circuit in a direction from the emitter terminal of the fifth transistor to the emitter terminal of the sixth transistor and an arrangement of the variable negative capacitance circuit in a direction from the emitter terminal of the sixth transistor to the emitter terminal of the fifth transistor are matched.

8. The amplifier circuit according to claim 1 , wherein the variable negative capacitance circuit further includes:
a seventh transistor between the fifth transistor and the first variable current source, the seventh transistor having a base terminal and a collector terminal connected to the emitter terminal of the fifth transistor and an emitter terminal connected to the first end of the first variable current source; and
an eighth transistor between the sixth transistor and the second variable current source, the eighth transistor having a base terminal and a collector terminal connected to the emitter terminal of the sixth transistor and an emitter terminal connected to the first end of the second variable current source.

9. The amplifier circuit according to claim 8 , wherein the variable degeneration circuit further includes:
a variable capacitance and a first resistor are connected in parallel between an emitter terminal of the first transistor and an emitter terminal of the second transistor.

10. The amplifier circuit according to claim 8 , wherein the variable degeneration circuit further includes:
a first resistor connected between an emitter terminal of the first transistor and an emitter terminal of the second transistor,
a first capacitor and a first variable resistor connected in series between an emitter terminal of the first transistor and an emitter terminal of the second transistor, and
a second variable resistor and a second capacitor connected in series between the emitter terminal of the first transistor and the emitter terminal of the second transistor.

11. The amplifier circuit according to claim 1 , further comprising:
a first current source transistor having a base terminal connected to a bias voltage, a collector terminal connected to the emitter terminal of the first transistor, and an emitter terminal connected to ground;
a second current source transistor having a base terminal connected to the bias voltage, a collector terminal connected to the emitter terminal of the second transistor, and an emitter terminal connected to ground;
a second resistor having a first end connected to the collector terminal of the first transistor and a second end connected to the power supply voltage;
a third resistor having a first end connected to the collector terminal of the second transistor and a second end connected to the power supply voltage;
a first constant current source having a first end connected to the emitter terminal of the third transistor and a second end connected to ground; and
a second constant current source having a first end connected to the emitter terminal of the fourth transistor and a second end connected to ground.

12. A driver circuit comprising the amplifier circuit according to claim 1 .

13. A driver circuit comprising:
a first amplifier circuit comprising:
a first transistor and a second transistor having a differential configuration in which base terminals of the first transistor and the second transistor are connected to differential input signal terminals of an amplifier circuit,
a third transistor having a base terminal connected to a collector terminal of the second transistor, a collector terminal connected to a power supply voltage, and an emitter terminal connected to a first output signal terminal on a positive phase side of an amplifier circuit;
a fourth transistor having a base terminal connected to a collector terminal of the first transistor, a collector terminal connected to the power supply voltage, and an emitter terminal connected to a second output signal terminal on an opposite phase side of the amplifier circuit,

a variable degeneration circuit connected to emitter terminals of the first transistor and the second transistor; and
a variable negative capacitance circu

Assignees

• Nippon Telegraph & Telephone

Inventors

• Jo Teruo
• Nagatani Munehiko
• Nosaka Hideyuki

Classifications

• H03F2200/36

  the amplifier comprising means for increasing the bandwidth · CPC title

• H03F3/45179

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

• H03G1/0029

  using field-effect transistors [FET] · CPC title

• H03F2203/45492

  the CSC being a pi circuit and the resistor being implemented by one or more controlled transistors · CPC title

• H03F2203/45488

  the CSC being a pi circuit and a capacitor being used at the place of the resistor · CPC title