Embeddable semiconductor-based capacitor

US12159945B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12159945-B2
Application numberUS-202217740412-A
CountryUS
Kind codeB2
Filing dateMay 10, 2022
Priority dateMay 14, 2021
Publication dateDec 3, 2024
Grant dateDec 3, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor-based capacitor can include a substrate including a semiconductor material, an oxide layer formed on a surface of the substrate, a conductive layer formed over at least a portion of the oxide layer, a plurality of distinct coplanar upper terminals, and at least one lower terminal formed. Each of the upper terminals and the at least one lower terminal can be exposed along the top and bottom surfaces of the substrate, respectively, for embedding the capacitor in a substrate such as a circuit board. The semiconductor-based capacitor can be sufficiently miniaturized to be embeddable within a circuit board while providing superior capacitance values. For example, a ratio of the length to the width of the substrate can be in a range from about 3:1 to about 1:3 and an area of the substrate can be less than about 3 mm 2 .

First claim

Opening claim text (preview).

What is claimed is: 1. An embeddable capacitor comprising: a substrate comprising a semiconductor material; a conductive layer formed over the substrate; an intervening layer between the substrate and the conductive layer, wherein the intervening layer comprises one or more of an oxide layer and an insulator layer; a plurality of distinct coplanar upper terminals formed over the conductive layer; a lower terminal formed over a bottom surface of the substrate opposite the top surface of the substrate; wherein the substrate has a length extending in a first direction and a width extending in a second direction perpendicular to the first direction, further wherein a ratio of the length to the width is in a range from about 3:1 to about 1:3 and an area of the substrate is less than about 3 mm 2 . 2. The capacitor of claim 1 , wherein the plurality of upper terminals and the lower terminal comprise at least one of copper, gold, or aluminum. 3. The capacitor of claim 1 , wherein each upper terminal comprises a thickness of at least about 5 microns. 4. The capacitor of claim 1 , wherein the lower terminal comprises a plurality of distinct coplanar lower terminals. 5. The capacitor of claim 4 , wherein the lower terminals are aligned with the upper terminals with respect to the first and second directions. 6. The capacitor of claim 1 , wherein the intervening layer comprises both the oxide layer and the insulator layer, wherein the insulator layer is formed over the oxide layer. 7. The capacitor of claim 6 , wherein the insulator layer comprises silicon nitride. 8. The capacitor of claim 1 , further comprising an upper protective layer formed over the conductive layer and a lower protective layer formed over the bottom surface of the substrate. 9. The capacitor of claim 8 , wherein each of the plurality of upper terminals extends through the upper protective layer in a vertical direction normal to the top surface of the substrate. 10. The capacitor of claim 1 , wherein each of the plurality of upper terminals are exposed along a top surface of the capacitor. 11. The capacitor of claim 1 , wherein the at least one lower terminal is exposed along a bottom surface of the capacitor. 12. The capacitor of claim 1 , wherein the semiconductor material of the substrate comprises silicon. 13. The capacitor of claim 1 , wherein the intervening layer comprises the oxide layer, further wherein the oxide layer comprises silicon oxide. 14. The capacitor of claim 1 , wherein the capacitor comprises a capacitance value in a range from about 0.1 pF to about 1800 pF. 15. A circuit board comprising: a substrate that defines a mounting surface, wherein a recessed opening is provided in the mounting surface; and a capacitor comprising: a semiconductor substrate; a plurality of distinct coplanar upper terminals formed over a top surface of the semiconductor substrate; a lower terminal formed over a bottom surface of the semiconductor substrate opposite the top surface of the substrate; wherein the semiconductor substrate has a length extending in a first direction and a width extending in a second direction perpendicular to the first direction, further wherein an area of the semiconductor substrate is less than about 3 mm 2 ; wherein the capacitor is embedded within the recessed opening. 16. The circuit board of claim 15 , wherein the capacitor further comprises an oxide layer formed on a top surface of the substrate and a conductive layer formed over the oxide layer. 17. The circuit board of claim 16 , wherein the plurality of distinct coplanar upper terminals are formed over the conductive layer. 18. The circuit board of claim 16 , further comprising an insulator layer formed between the oxide layer and the conductive layer. 19. The circuit board of claim 15 , wherein the at least one lower terminal comprises a plurality of distinct coplanar lower terminals. 20. A method of embedding a capacitor in a substrate comprising: providing a substrate, wherein the substrate comprises a recessed opening in a surface of the substrate; providing a capacitor, wherein the capacitor comprises: a semiconductor substrate; a plurality of distinct coplanar upper terminals formed over a top surface of the semiconductor substrate; at least one lower terminal formed over a bottom surface of the semiconductor substrate opposite the top surface of the substrate; wherein the semiconductor substrate has a length extending in a first direction and a width extending in a second direction perpendicular to the first direction, further wherein an area of the semiconductor substrate is less than about 3 mm 2 ; inserting the capacitor within the recessed opening; and electrically connecting the substrate with at least one of the upper terminals of the capacitor.

Assignees

Inventors

Classifications

  • of conductor-insulator-semiconductor capacitors, e.g. trench capacitors · CPC title

  • Electrodes · CPC title

  • H10D1/66Primary

    Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors · CPC title

  • associated with components mounted in and supported by recessed areas of the PCBs · CPC title

  • electrically connecting electric components or wires to printed circuits · CPC title

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What does patent US12159945B2 cover?
A semiconductor-based capacitor can include a substrate including a semiconductor material, an oxide layer formed on a surface of the substrate, a conductive layer formed over at least a portion of the oxide layer, a plurality of distinct coplanar upper terminals, and at least one lower terminal formed. Each of the upper terminals and the at least one lower terminal can be exposed along the top…
Who is the assignee on this patent?
Kyocera Avx Components Corp
What technology area does this patent fall under?
Primary CPC classification H10D1/66. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 03 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).