Semiconductor device with semiconductor mesas between adjacent gate trenches

Patent metadata

Field	Value
Publication number	US-12159933-B2
Application number	US-202318453717-A
Country	US
Kind code	B2
Filing date	Aug 22, 2023
Priority date	Jun 21, 2021
Publication date	Dec 3, 2024
Grant date	Dec 3, 2024

Abstract

A semiconductor device is described. The semiconductor device includes: a semiconductor substrate having a first main surface; a plurality of gate trenches extending from the first main surface into the semiconductor substrate; a semiconductor mesa between adjacent gate trenches; a first interlayer dielectric on the first main surface; a plurality of first metal contacts extending through the first interlayer dielectric and contacting gate electrodes disposed in the gate trenches; a plurality of second metal contacts extending through the first interlayer dielectric and contacting the semiconductor mesas; and an air gap or a dielectric material having a lower dielectric constant than the first interlayer dielectric between adjacent first and second metal contacts. Methods of producing the semiconductor device are also described.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate having a first main surface;
a plurality of gate trenches extending from the first main surface into the semiconductor substrate;
a semiconductor mesa between adjacent gate trenches;
a first interlayer dielectric on the first main surface;
a plurality of first metal contacts extending through the first interlayer dielectric and contacting gate electrodes disposed in the gate trenches;
a plurality of second metal contacts extending through the first interlayer dielectric and contacting the semiconductor mesas; and
an air gap or a dielectric material having a lower dielectric constant than the first interlayer dielectric between adjacent first and second metal contacts.

2. The semiconductor device of claim 1 , wherein the air gap is between the adjacent first and second metal contacts.

3. The semiconductor device of claim 2 , wherein the distance between the adjacent first and second metal contacts occupied by the air gap is less than or equal to 200 nm.

4. The semiconductor device of claim 1 , wherein the first metal contacts extend into the gate electrodes and have a first part in the gate electrodes and a second part in the first interlayer dielectric and that is wider than the first part, wherein the second metal contacts extend into the semiconductor mesas and have a first part in the semiconductor mesas and a second part in the first interlayer dielectric and that is wider than the first part, and wherein the air gap or the dielectric material having the lower dielectric constant is between the second part of the adjacent first and second metal contacts.

5. The semiconductor device of claim 4 , wherein the first metal contacts further have a third part above the second part and that is wider than the second part, wherein the second metal contacts further have a third part above the second part and that is wider than the second part, and wherein the air gap or the dielectric material having the lower dielectric constant is between both the second part and the third part of the adjacent first and second metal contacts.

6. The semiconductor device of claim 1 , wherein the air gap or the dielectric material having the lower dielectric constant has a negative taper relative to the semiconductor substrate such that the air gap or the dielectric material having the lower dielectric constant is wider closer to the semiconductor substrate and narrower further from the semiconductor substrate.

7. The semiconductor device of claim 1 , wherein a space between the adjacent first and second metal contacts has an aspect ratio of at least 3:1 where the aspect ratio relates vertical height of the space to lateral width of the space between the adjacent first and second metal contacts.

8. The semiconductor device of claim 1 , wherein the first interlayer dielectric comprises a first oxide layer in contact with the first main surface of the semiconductor substrate, a silicon nitride layer on the first oxide layer, and a second oxide layer on the silicon nitride layer, and wherein the second oxide layer is thicker than the first oxide layer.

9. The semiconductor device of claim 1 , wherein the first metal contacts comprise tungsten, wherein the second metal contacts comprise tungsten, and wherein the gate electrodes comprise polysilicon.

10. The semiconductor device of claim 1 , wherein the first metal contacts, the second metal contacts, and the gate electrodes each comprise tungsten.

11. The semiconductor device of claim 1 , wherein each semiconductor mesa includes a source region of a first conductivity type and a body region of a second conductivity type, wherein the source region and the body region included in the same semiconductor mesa form part of a transistor cell, and wherein the transistor cells are electrically connected in parallel to form a transistor.

12. The semiconductor device of claim 1 , further comprising a plurality of field plates below and insulated from the gate electrodes in the gate trenches, or in field plate trenches that are separate from the gate trenches.

13. The semiconductor device of claim 1 , further comprising:
a second interlayer dielectric on the first interlayer dielectric;
a plurality of third metal contacts extending through the second interlayer dielectric and contacting the first metal contacts; and
a plurality of fourth metal contacts extending through the second interlayer dielectric and contacting the second metal contacts,
wherein a material of the second interlayer dielectric seals the air gap between the adjacent first and second metal contacts.

14. A method of producing a semiconductor device, the method comprising:
forming a plurality of gate trenches extending from a first main surface of a semiconductor substrate into the semiconductor substrate such that a semiconductor mesa is arranged between adjacent gate trenches;
forming a first interlayer dielectric on the first main surface;
forming a plurality of first metal contacts extending through the first interlayer dielectric and contacting gate electrodes disposed in the gate trenches;
forming a plurality of second metal contacts extending through the first interlayer dielectric and contacting the semiconductor mesas; and
forming an air gap or a dielectric material having a lower dielectric constant than the first interlayer dielectric between adjacent first and second metal contacts.

15. The method of claim 14 , wherein forming the air gap comprises:
etching the first interlayer dielectric between the adjacent first and second metal contacts; and
after the etching, depositing an oxide using a chemical vapor deposition process or by sputtering,
wherein the oxide seals the air gap between the adjacent first and second metal contacts.

16. The method of claim 15 , further comprising:
continuing the chemical vapor deposition process or the sputtering after the oxide seals the air gap between the adjacent first and second metal contacts, to form a second interlayer dielectric on the first interlayer dielectric.

17. The method of claim 16 , further comprising:
forming a plurality of third metal contacts extending through the second interlayer dielectric and contacting the first metal contacts; and
forming a plurality of fourth metal contacts extending through the second interlayer dielectric and contacting the second metal contacts.

18. The method of claim 14 , wherein the etching is implemented as a timed etching process that stops after a predetermined amount of time lapses.

19. The method of claim 14 , wherein the first interlayer dielectric comprises a first oxide layer in contact with the first main surface of the semiconductor substrate, a silicon nitride layer on the first oxide layer, and a second oxide layer on the silicon nitride layer, wherein the second oxide layer is thicker than the first oxide layer, and wherein the etching stops when the silicon nitride layer is detected.

20. The method of claim 14 , wherein the first interlayer dielectric is etched in a first region and protected from the etching in a second region such that the air gap is provided in the first region but not in the second region.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Brazzale Anita
• Haase Robert
• Leomant Sylvain
• Naik Harsh

Classifications

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/0698

  Local interconnections · CPC title