Nitride-based multi-channel switching semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-12159871-B2
Application number	US-202117625094-A
Country	US
Kind code	B2
Filing date	Jul 1, 2021
Priority date	Jul 1, 2021
Publication date	Dec 3, 2024
Grant date	Dec 3, 2024

Abstract

The present invention provides a nitride-based multi-channel switching device having a plurality of transistors. The multi-channel switching device comprises a substrate, a plurality gate structures, a plurality of source electrodes and a plurality of drain electrodes. The gate structures, source electrodes and drain electrodes are grouped to form the plurality of transistors and arranged such that each gate structure disposed between a source electrode and drain electrode. Each group of the gate structures are electrically interconnected and connected to at least one gate pad corresponding to each of the transistor. Each group of the drain electrode are electrically interconnected and connected to at least one drain pad corresponding to each of the transistor. All groups of the source electrodes are electrically interconnected and connected to at least one common source pad.

First claim

The invention claimed is:

1. A nitride-based multi-channel switching device having a plurality of transistors and comprising:
a substrate;
a buffer structure disposed over the substrate;
a first nitride-based semiconductor layer disposed over the buffer structure;
a second nitride-based semiconductor layer disposed over the first nitride-based semiconductor layer and having a bandgap greater than the bandgap of the first nitride-based semiconductor layer; and
a plurality gate structures disposed above the second nitride-based semiconductor layer;
a first passivation layer disposed on the second nitride-based semiconductor layer and covering the gate structures;
a plurality of source electrodes disposed on the second nitride-based semiconductor layer and penetrating through the first passivation layer;
a plurality of drain electrodes disposed on the second nitride-based semiconductor layer and penetrating through the first passivation layer;
a second passivation layer disposed on the first passivation layer and covering the source electrodes and drain electrodes;
one or more conductive vias disposed within the second passivation layer;
a conductive layer disposed on the second passivation layer and patterned to form one or more conductive traces;
a protection layer disposed above the conductive layer and having one or more openings to expose one or more conductive pads to form a plurality of drain pads respectively corresponding to the plurality of transistors, a plurality of gate pads respectively corresponding to the plurality of transistors and at least one common source pad;
wherein
the gate structures, source electrodes and drain electrodes are grouped to form the plurality of transistors and arranged such that each gate structure disposed between a source electrode and drain electrode; and
each group of the gate structures are electrically interconnected and connected to at least one gate pad corresponding to each of the transistor;
each group of the drain electrode are electrically interconnected and connected to at least one drain pad corresponding to each of the transistor;
all groups of the source electrodes are electrically interconnected and connected to at least one common source pad.

2. The nitride-based multi-channel switching device according to claim 1 , wherein each of the plurality of transistors comprises a heterojunction that is formed between first and second nitride-based semiconductor layers with a two-dimensional electron gas (2DEG) region adjacent to the heterojunction.

3. The nitride-based multi-channel switching device according to claim 1 , wherein the buffer structure comprises:
at least one first layer of a doped nitride-based semiconductor compound at a top-most portion thereof; and
a second layer located between the substrate and the first layer and including a nitride-based semiconductor compound which has a composition different than the doped nitride-based semiconductor compound.

4. The nitride-based multi-channel switching device according to claim 3 , wherein the doped nitride-based semiconductor compound of the buffer structure is a p-type gallium nitride-based semiconductor compound.

5. The nitride-based multi-channel switching device according to claim 4 , wherein the p-type gallium nitride-based semiconductor compound is carbon-doped gallium nitride.

6. The nitride-based multi-channel switching device according to claim 1 , wherein the first nitride-based semiconductor layer and the second nitride-based semiconductor layer comprise gallium.

7. The nitride-based multi-channel switching device according to claim 1 , wherein the plurality of transistors is arranged in a one-dimensional array.

8. The nitride-based multi-channel switching device according to claim 1 , wherein the plurality of transistors is arranged in a two-dimensional array.

9. A method for manufacturing a nitride-based multi-channel switching device having a plurality of transistors, the method comprising:
forming a buffer structure over a substrate;
forming a first nitride-based semiconductor layer disposed over the buffer structure;
forming a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer;
disposing a gate semiconductor layer on the second nitride-based semiconductor layer and a gate electrode layer on the gate semiconductor layer, and patterning the gate semiconductor layer and the gate electrode layer to form one or more gate structures;
forming a first passivation layer on the second nitride-based semiconductor layer to cover the gate structures; forming one or more openings in the first passivation layer to expose some regions of the second nitride-based semiconductor layer, disposing a source/drain electrode layer to cover the first passivation layer and exposed regions of the second nitride-based semiconductor layer, and patterning the source/drain electrode layer to form one or more source/drain electrodes penetrating through the first passivation layer and in contact with the second nitride-based semiconductor layer;
forming a second passivation layer on the first passivation layer to cover the source/drain electrodes;
forming one or more conductive vias within the second passivation layer;
forming a conductive layer on the second passivation layer and patterning the conductive layer to form one or more patterned conductive traces; and
forming a protection layer above the conductive layer and patterning the protection layer to form one or more openings to expose one or more conductive pads to form a plurality of drain pads respectively corresponding to the plurality of transistors, a plurality of gate pads respectively corresponding to the plurality of transistors and at least one common source pad;
wherein:
the plurality of gate structures, source electrodes and drain electrodes are grouped to form the plurality of transistors such that each transistor having at least one gate structure disposed between at least one source electrode and at least one drain electrode; and
each group of the gate structures are electrically interconnected and connected to at least one gate pad corresponding to each of the transistor;
each group of the drain electrode are electrically interconnected and connected to at least one drain pad corresponding to each of the transistor;
all groups of the source electrodes are electrically interconnected and connected to at least one common source pad.

10. The method according to claim 9 , wherein each of the plurality of transistors is formed such that a heterojunction is formed between first and second nitride-based semiconductor layers with a two-dimensional electron gas (2DEG) region adjacent to the heterojunction.

11. The method according to claim 9 , wherein forming the buffer structure comprises:
forming at least one first layer of a doped nitride-based semiconductor compound at a top-most portion thereof; and
forming a second layer located between the substrate and the first layer and including a nitride-based semiconductor compound which has a composition different than the doped nitride-based semiconductor compound.

Assignees

• Innoscience Suzhou Technology Holding Co Ltd

Inventors

• Yan Hui
• Li sichao
• Cai Dinghui
• Li Jihua
• Chen Yulin
• Zhang Tao

Classifications

• H10W74/147

  the encapsulations being multilayered · CPC title

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D88/01

  Manufacture or treatment · CPC title

• H10D84/0123

  Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs · CPC title