Data co-location using address hashing for high-performance processing in memory

Patent metadata

Field	Value
Publication number	US-12158842-B2
Application number	US-202217956995-A
Country	US
Kind code	B2
Filing date	Sep 30, 2022
Priority date	Sep 30, 2022
Publication date	Dec 3, 2024
Grant date	Dec 3, 2024

Abstract

A processing system allocates memory to co-locate input and output operands for operations for processing in memory (PIM) execution in the same PIM-local memory while exploiting row-buffer locality and complying with conventional memory abstraction. The processing system identifies as “super rows” virtual rows that span all the banks of a memory device. Each super row has a different bank-interleaving pattern, referred to as a “color”. A group of contiguous super rows that has the same PIM-interleaving pattern is referred to as a “color group”. The processing system assigns memory addresses to each operand (e.g., vector) of an operation for PIM execution to a super row having a different color within the same color group to co-locate the operands for each PIM execution unit and uses address hashing to alternate between banks assigned to elements of a first operand and elements of a second operand of the operation.

First claim

What is claimed is:

1. A processing system, comprising:
a plurality of processing in memory (PIM) execution units configured to interface with a memory that has a plurality of banks, wherein each PIM execution unit corresponds to a group of banks; and
a processor configured to:
assign an interleaving pattern to each super row of the memory, wherein each super row is a virtual row that spans all the banks of the memory; and
allocate memory addresses to a set of operands for an operation performed by a first PIM execution unit, wherein each operand is assigned to a super row having a different interleaving pattern and all the operands in the set are allocated to super rows in a same color group.

2. The processing system of claim 1 , wherein the processor is to assign the set of operands to the group of banks associated with the first execution unit.

3. The processing system of claim 2 , wherein each operand comprises a plurality of elements, and wherein the processor is to hash the memory addresses to map elements of the operands with a same index to different banks of the memory.

4. The processing system of claim 1 , wherein the processor is to configure a row identification field of a memory address of an operand to indicate the color group that includes the super row of the operand and to indicate the bank interleaving pattern of the super row of the operand.

5. The processing system of claim 4 , wherein the processor is to configure an offset field of the memory address of the operand to indicate which element of the operand is located at which bank and row of the color group and the bank interleaving pattern of the super row of the operand.

6. The processing system of claim 1 , wherein the memory processor is to allocate an operand to two or more contiguous super rows in response to the operand exceeding a size of a super row.

7. A processing system, comprising:
a plurality of processing in memory (PIM) execution units configured to interface with a memory that has a plurality of banks, wherein each PIM execution unit corresponds to a group of banks; and
a processor configured to:
assign an interleaving pattern to each super row of the memory, wherein each super row is a virtual row that spans all the banks of the memory; and
allocate memory addresses to a set of operands for an operation performed by a first PIM execution unit, wherein each operand is assigned to a super row having a different interleaving pattern and all the operands in the set are allocated to super rows in a same color group.

8. The processing system of claim 7 , wherein the processor is to assign the set of operands to the group of banks associated with the first PIM execution unit.

9. The method of claim 8 , wherein each operand comprises a plurality of elements, and wherein allocating the memory addresses comprises hashing the memory addresses to map elements of the operands with a same index to different banks of the memory.

10. The processing system of claim 7 , wherein the processor is to configure a row identification field of a memory address of an operand to indicate the color group that includes the super row of the operand and to indicate the interleaving pattern of the super row of the operand.

11. The processing system of claim 10 , wherein the processor is to configure an offset field of the memory address of the operand to indicate which element of the operand is located at which bank and row of the color group and the interleaving pattern of the super row of the operand.

12. The method of claim 7 , further comprising wherein allocating the memory addresses comprises:
in response to an operand exceeding a size of a super row, allocating the operand to two or more contiguous super rows within the group of super rows.

13. The method of claim 12 , further comprising:
alternating a sequence of the interleaving patterns of the two or more contiguous super rows within the group of super rows in response to the operand being allocated to a super row having an interleaving pattern that is not a first interleaving pattern in the group of super rows.

14. The method of claim 13 , wherein allocating the memory addresses comprises assigning the set of operands to the group of banks associated with the first PIM execution unit.

15. The method of claim 14 , wherein mapping the first vector and the second vector comprises assigning the first vector and the second vector to the group of banks associated with the first PIM execution unit.

16. The method of claim 15 , wherein assigning the first vector and the second vector comprises hashing memory addresses assigned to the first vector and the second vector to map elements of the first vector and the second vector with a same index to different banks of the memory.

17. The method of claim 14 , further comprising configuring a row identification field of a memory address of the first vector to indicate the first group of super rows that includes the first super row and to indicate the first interleaving pattern of the first super row.

18. The method of claim 13 , wherein allocating the memory addresses comprises:
in response to an operand exceeding a size of a super row, allocating the operand to two or more contiguous super rows within the group of super rows.

19. The method of claim 14 , further comprising:
allocating to the first vector to a first plurality of contiguous super rows in the first group of super rows in response to the first vector exceeding a size of the first super row.

20. The method of claim 19 , further comprising:
alternating a sequence of interleaving patterns within the first group of super rows in response to a first super row of the first plurality of contiguous super rows having an interleaving pattern that is not the first interleaving pattern in the first group of super rows.

Assignees

• Advanced Micro Devices Inc

Inventors

• Cho Benjamin Youngjae
• Behroozi Armand Bahram
• Chu Michael L
• Aji Ashwin

Classifications

• G06F12/0223

  User address space allocation, e.g. contiguous or non contiguous base addressing · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F12/0607 Primary

  Interleaved addressing · CPC title