Storing memory array operational information in non-volatile subarrays

Patent metadata

Field	Value
Publication number	US-12158826-B2
Application number	US-202217853321-A
Country	US
Kind code	B2
Filing date	Jun 29, 2022
Priority date	Sep 16, 2016
Publication date	Dec 3, 2024
Grant date	Dec 3, 2024

Abstract

Methods, systems, and apparatuses for storing operational information related to operation of a non-volatile array are described. For example, the operational information may be stored in a in a subarray of a memory array for use in analyzing errors in the operation of memory array. In some examples, an array driver may be located between a command decoder and a memory array. The array driver may receive a signal pattern used to execute an access instruction for accessing non-volatile memory cells of a memory array and may access the first set of non-volatile memory cells according to the signal pattern. The array driver may also store the access instruction (e.g., the binary representation of the access instruction) at a non-volatile subarray of the memory array.

First claim

What is claimed is:

1. A method, comprising:
entering a test mode for storing data in a first portion of a memory array, the data representative of a pattern of a plurality of instructions received, at a command decoder from a host device, for accessing a second portion of the memory array;
accessing the second portion of the memory array according to the plurality of instructions for accessing the second portion of the memory array;
storing, in a set of non-volatile memory cells of the first portion of the memory array, the data representative of the pattern of the plurality of instructions for accessing the second portion based at least in part on entering the test mode; and
communicating the data representative of the pattern of the plurality of instructions from the first portion of the memory array to the command decoder based at least in part on storing the data representative of the pattern of the plurality of instructions in the set of non-volatile memory cells.

2. A method, comprising:
entering a test mode for storing data in a first portion of a memory array, the data associated with instructions for accessing a second portion of the memory array;
accessing the second portion of the memory array according to the instructions for accessing the second portion of the memory array;
storing, in a set of non-volatile memory cells of the first portion of the memory array, the data associated with the instructions for accessing the second portion of the memory array based at least in part on entering the test mode;
accessing one or more memory cells of the set of non-volatile memory cells of the first portion of the memory array based at least in part on entering the test mode; and
determining that a first error associated with the memory array has occurred based at least in part on accessing the one or more memory cells of the set of non-volatile memory cells of the first portion of the memory array.

3. The method of claim 1 , further comprising:
receiving a first command, wherein entering the test mode is based at least in part on receiving the first command.

4. The method of claim 1 , further comprising:
receiving a second command based at least in part on the memory array receiving a quantity of commands within a duration, wherein entering the test mode is based at least in part on receiving the second command.

5. The method of claim 1 , further comprising:
receiving a third command from an application that has experienced an operating error, wherein entering the test mode is based at least in part on receiving the third command.

6. The method of claim 1 , further comprising:
receiving, from an error correction code (ECC) component, a fourth command based at least in part on a quantity of errors occurring at the memory array, wherein entering the test mode is based at least in part on receiving the fourth command.

7. The method of claim 1 , wherein accessing the second portion of the memory array and storing the data in the set of non-volatile memory cells of the first portion of the memory array occur during a same duration.

8. The method of claim 1 , wherein the first portion of the memory array comprises a subarray of the memory array.

9. A method, comprising:
entering a test mode for storing data in a first portion of a memory array, the data associated with instructions for accessing a second portion of the memory array, wherein the second portion of the memory array comprises a set of volatile memory cells;
accessing the second portion of the memory array according to the instructions for accessing the second portion of the memory array; and
storing, in a set of non-volatile memory cells of the first portion of the memory array, the data associated with the instructions for accessing the second portion of the memory array based at least in part on entering the test mode.

10. The method of claim 1 , wherein the second portion of the memory array comprises a second set of non-volatile memory cells.

11. An apparatus, comprising:
a memory array comprising a plurality of memory cells;
an array driver; and
one or more controllers in electronic communication with the memory array and the array driver, wherein the one or more controllers is configured to cause the apparatus to:
enter a test mode for storing data in a first portion of the memory array, the data representative of a pattern of a plurality of instructions received, at a command decoder from a host device, for accessing a second portion of the memory array;
access the second portion of the memory array according to the plurality of instructions for accessing the second portion of the memory array;
store, in a set of non-volatile memory cells of the first portion of the memory array, the data representative of the pattern of the plurality of instructions for accessing the second portion based at least in part on entering the test mode; and
communicate the data representative of the pattern of the plurality of instructions from the first portion of the memory array to the command decoder based at least in part on storing the data representative of the pattern of the plurality of instructions in the set of non-volatile memory cells.

12. An apparatus comprising:
a memory array comprising a plurality of memory cells;
an array driver; and
one or more controllers in electronic communication with the memory array and the array driver, wherein the one or more controllers are configured to cause the apparatus to:
enter a test mode for storing data in a first portion of the memory array, the data comprising a representation of a pattern of instructions received from a host device for accessing a second portion of the memory array;
access the second portion of the memory array according to the instructions for accessing the second portion of the memory array;
store, in a set of non-volatile memory cells of the first portion of the memory array, the data based at least in part on entering the test mode;
access one or more memory cells of the set of non-volatile memory cells of the first portion of the memory array based at least in part on entering the test mode; and
determine that a first error associated with the memory array has occurred based at least in part on accessing the one or more memory cells of the set of non-volatile memory cells of the first portion of the memory array.

13. The apparatus of claim 11 , wherein the one or more controllers is further configured to cause the apparatus to:
receive a first command, wherein entering the test mode is based at least in part on receiving the first command.

14. The apparatus of claim 11 , wherein the one or more controllers is further configured to cause the apparatus to:
receive a second command based at least in part on the memory array receiving a quantity of commands within a duration, wherein entering the test mode is based at least in part on receiving the second command.

15. The apparatus of claim 11 , wherein the one or more controllers is further configured to cause the apparatus to:
receive a third command from an application that has experienced an operating error, wherein entering the test mode is based at least in part on receiving the third command.

16. The apparatus of claim 11 , wherein the one or more controllers is further configured to cause the apparatus to:
receive, from an error correction code (ECC) component, a fourth command based at least in part on a quantity of errors occurring at the memory array, wherein entering the test mode is based at least in part on receiving the fourth command.

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Assignees

• Micron Technology Inc

Inventors

• Kawamura Christopher John
• Derner Scott James
• Ingalls Charles L

Classifications

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C11/2275

  Writing or programming circuits or methods · CPC title

• G11C11/2273

  Reading or sensing circuits or methods · CPC title

• G11C11/2257

  Word-line or row circuits · CPC title

• G11C11/2255

  Bit-line or column circuits · CPC title