Signal detector circuit and signal detection method

US12158484B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12158484-B2
Application numberUS-202217953274-A
CountryUS
Kind codeB2
Filing dateSep 26, 2022
Priority dateFeb 17, 2022
Publication dateDec 3, 2024
Grant dateDec 3, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A signal detector circuit includes a signal peak detector circuit, a reference voltage generation circuit, and a comparator circuit. The signal peak detector circuit is arranged to receive a plurality of differential voltage input signals, and generate a single-ended peak signal according to the plurality of differential voltage input signals. The reference voltage generation circuit is arranged to generate a single-ended reference voltage signal. The comparator circuit is arranged to receive the single-ended peak signal and the single-ended reference voltage signal, and compare the single-ended peak signal with the single-ended reference voltage signal to generate a signal detection result.

First claim

Opening claim text (preview).

What is claimed is: 1. A signal detector circuit, comprising: a signal peak detector circuit, arranged to receive a plurality of differential voltage input signals, and generate a single-ended peak signal according to the plurality of differential voltage input signals; a reference voltage generation circuit, arranged to generate a single-ended reference voltage signal; and a comparator circuit, arranged to receive the single-ended peak signal and the single-ended reference voltage signal, and compare the single-ended peak signal with the single-ended reference voltage signal, to generate a signal detection result; wherein the signal peak detector circuit comprises multiple switch circuits, and the signal peak detector circuit samples and holds the plurality of differential voltage input signals by conducting the multiple switch circuits, to generate the single-ended peak signal. 2. The signal detector circuit of claim 1 , wherein the plurality of differential voltage input signals comprises a first differential voltage input signal and a second differential voltage input signal, and the multiple switch circuits comprise: a first switch circuit, having a first end and a second end, wherein the first end of the first switch circuit is arranged to receive the first differential voltage input signal, and the first switch circuit is conductive according to a first control signal, for transmitting the first differential voltage input signal to the second end of the first switch circuit; and a second switch circuit, having a first end and a second end, wherein the first end of the second switch circuit is arranged to receive the second differential voltage input signal, and the second switch circuit is conductive according to a second control signal, for transmitting the second differential voltage input signal to the second end of the second switch circuit; wherein the signal peak detector circuit further comprises: a capacitance, having a first end and a second end, and arranged to output the single-ended peak signal, wherein the first end of the capacitance is coupled to the second end of the first switch circuit and the second end of the second switch circuit, and the second end of the capacitance is coupled to a reference voltage. 3. The signal detector circuit of claim 2 , wherein the first control signal is the second differential voltage input signal, and the second control signal is the first differential voltage input signal. 4. The signal detector circuit of claim 3 , wherein when the first differential voltage input signal is a first level and the second differential voltage input signal is a second level that is lower than the first level, the first switch circuit is conductive and the second switch circuit is not conductive, and the single-ended peak signal is the first differential voltage input signal. 5. The signal detector circuit of claim 3 , wherein when the first differential voltage input signal is a first level and the second differential voltage input signal is a second level that is higher than the first level, the first switch circuit is not conductive and the second switch circuit is conductive, and the single-ended peak signal is the second differential voltage input signal. 6. A signal detection method, comprising: receiving a plurality of differential voltage input signals; generating a single-ended peak signal according to the plurality of differential voltage input signals; generating a single-ended reference voltage signal; and comparing the single-ended peak signal with the single-ended reference voltage signal to generate a signal detection result; wherein generating the single-ended peak signal according to the plurality of differential voltage input signals comprises: sampling and holding the plurality of differential voltage input signals by conducting multiple switch circuits, to generate the single-ended peak signal. 7. The signal detection method of claim 6 , wherein the plurality of differential voltage input signals comprises a first differential voltage input signal and a second differential voltage input signal, the multiple switch circuits comprise a first switch circuit and a second switch circuit; and sampling and holding the plurality of differential voltage input signals by conducting the multiple switch circuits, to generate the single-ended peak signal comprises: conducting the first switch circuit according to a first control signal, for transmitting the first differential voltage input signal to a first end of a capacitance; and conducting the second switch circuit according to a second control signal, for transmitting the second differential voltage input signal to the first end of the capacitance; wherein the capacitance is arranged to output the single-ended peak signal, and a second end of the capacitance is coupled to a reference voltage. 8. The signal detection method of claim 7 , wherein the first control signal is the second differential voltage input signal and the control signal is the first differential voltage input signal. 9. The signal detection method of claim 8 , wherein when the first differential voltage input signal is a first level and the second differential voltage input signal is a second level that is lower than the first level, the first switch circuit is conductive and the second switch circuit is not conductive, and the single-ended peak signal is the first differential voltage input signal. 10. The signal detection method of claim 8 , wherein when the first differential voltage input signal is a first level and the second differential voltage input signal is a second level that is higher than the first level, the first switch circuit is not conductive and the second switch circuit is conductive, and the single-ended peak signal is the second differential voltage input signal.

Assignees

Inventors

Classifications

  • G01R19/04Primary

    Measuring peak values {or amplitude or envelope} of AC or of pulses · CPC title

  • comparing DC or AC voltage with one threshold (G01R19/16514, G01R19/16519, G01R19/16528, G01R19/16533 and G01R19/1659 take precedence) · CPC title

  • for individual pulses, ripple or noise and other applications where timing or duration is of importance (G01R19/16519, G01R19/16538 and G01R19/16595 take precedence; for pulse duration and rise time, see G01R29/02 and subgroups) · CPC title

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What does patent US12158484B2 cover?
A signal detector circuit includes a signal peak detector circuit, a reference voltage generation circuit, and a comparator circuit. The signal peak detector circuit is arranged to receive a plurality of differential voltage input signals, and generate a single-ended peak signal according to the plurality of differential voltage input signals. The reference voltage generation circuit is arrange…
Who is the assignee on this patent?
Realtek Semiconductor Corp
What technology area does this patent fall under?
Primary CPC classification G01R19/04. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 03 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).