Processor with block cipher algorithm, and a data encryption and decryption method operated by the processor

Patent metadata

Field	Value
Publication number	US-12155751-B2
Application number	US-202217837674-A
Country	US
Kind code	B2
Filing date	Jun 10, 2022
Priority date	Sep 1, 2021
Publication date	Nov 26, 2024
Grant date	Nov 26, 2024

Abstract

A processor with a block cipher algorithm and a data encryption and decryption method operated by the processor are shown. The processor uses a register to store an input key pointer pointing to an input key. In response to one single block cipher instruction of an instruction set architecture (ISA), the processor obtains input data from a first system memory area, performs the block cipher algorithm on the input data based on the input key indicated by the input key pointer stored in the register to encrypt or decrypt the input data to generate output data, and stores the output data in a second system memory area, or an internal storage area within the processor.

First claim

What is claimed is:

1. A processor with a block cipher algorithm, comprising:
a first register, storing an input key pointer pointing to an input key; and
a third register storing a control word that includes a plurality of mode setting bits for setting the block cipher algorithm to operate in an electronic code book mode, a cipher block chaining mode, a cipher feedback mode, an output feedback mode, and a counter mode;
wherein, in response to one single block cipher instruction, the processor reads input data from a first system memory area, performs the block cipher algorithm on the input data based on the input key to encrypt or decrypt the input data to generate output data, and stores the output data in a second system memory area or an internal storage area within the processor.

2. The processor as claimed in claim 1 , wherein:
the single block cipher instruction is executed according to the input key pointer pointing to the input key, an input data pointer pointing to the input data, and an output pointer indicating where to store the output data.

3. The processor as claimed in claim 1 , wherein:
according to an amount of input blocks carried in the input data, the processor divides the input data into input blocks;
the processor performs N rounds of calculation on each input block to transform each input block into an output block, the output blocks corresponding to the different input blocks are combined to form the output data, and N is an integer; and
based on the input key, the processor generates N extension keys corresponding to the N rounds of calculation.

4. The processor as claimed in claim 3 , further comprising:
a second register, storing the amount of input blocks carried in the input data.

5. The processor as claimed in claim 1 , wherein:
the third register further stores an encryption and decryption setting bit for setting the processor that operates according to the block cipher algorithm to encrypt or decrypt the input data based on the input key.

6. The processor as claimed in claim 1 , further comprising:
a fourth register, storing an input data pointer pointing to the first system memory area,
wherein, along with the execution of the block cipher algorithm, the processor increases the input data pointer stored in the fourth register according to a byte number of the input data.

7. The processor as claimed in claim 6 , further comprising:
a fifth register, storing an output data pointer pointing to the second system memory area,
wherein, along with the execution of the block cipher algorithm, the processor increases the output data pointer stored in the fifth register according to a byte number of the output data.

8. The processor as claimed in claim 1 , further comprising:
a fourth register, storing an input and output information pointer pointing to a third system memory area that stores an input data pointer pointing to the first system memory arca and an output data pointer pointing to the second system memory area.

9. The processor as claimed in claim 1 , wherein:
an input data pointer pointing to the first system memory area and an output data pointer pointing to the second system memory area are entered as two operands of the single block cipher instruction.

10. The processor as claimed in claim 1 , further comprising:
an encryption and decryption unit;
a set of architectural registers which provides the first register;
a microcode storage device, storing microcode; and
a decoder, transforming the single block cipher instruction into a plurality of microinstructions based on the microcode,
wherein:
according to the plurality of microinstructions, the set of architectural registers is read and managed, and the encryption and decryption unit performs the block cipher algorithm on the input data based on the input key.

11. The processor as claimed in claim 10 , wherein:
the encryption and decryption unit includes a block cipher engine;
the plurality of microinstructions include an engine driving microinstruction; and
in response to the engine driving microinstruction, the block cipher engine performs N rounds of calculation on each input block of the input data to transform each input block into one output block, wherein the output blocks corresponding to the different input blocks are combined to form the output data, and N is an integer.

12. The processor as claimed in claim 11 , wherein the block cipher engine comprises:
hardware for a key extension logic, receiving the input key, and transforming the input key into N extended keys to correspond to the N rounds of calculation of each input block; and
a first internal storage space, storing the N extended keys as N sequential keys for encryption in the generation order of the N extended keys, wherein the first internal storage space is in the block cipher engine.

13. The processor as claimed in claim 12 , wherein the block cipher engine further comprises:
hardware for anti-tone transform for keys, reversing the order of the N sequential keys read from the first internal storage space to generate N reversed-order keys; and
a second internal storage space, storing the N reversed-order keys for decryption, wherein the second internal storage space is in the block cipher engine.

14. The processor as claimed in claim 13 , wherein the block cipher engine further comprises:
a multiplexer, and hardware for a routine logic, wherein the multiplexer outputs the N sequential keys read from the first internal storage space or the N reversed-order keys read from the second internal storage space to the routine logic, and, according to the N sequential keys or the N reversed-order keys transferred from the multiplexer, the routine logic performs the N rounds of calculation on each input block to transform each input block into an output block; and
hardware for control logic, wherein, when an encryption and decryption setting bit indicates an encryption operation, the control logic operates the multiplexer to transfer the N sequential keys to the routine logic, and when the encryption and decryption setting bit indicates a decryption operation, the control logic operates the multiplexer to transfer the N reversed-order keys to the routine logic.

15. The processor as claimed in claim 13 , wherein:
the hardware for key extension logic comprises hardware for key-XOR logic, hardware for multi-XOR logic, hardware for non-linear transform, hardware for linear transform, and hardware for single XOR logic, which are connected in series.

16. The processor as claimed in claim 15 , wherein the block cipher engine further comprises:
a third internal storage space, storing a system parameter FK, and a fixed parameter CK;
FK is (FK 0 , FK 1 , FK 2 , FK 3 ), where FK 0 , FK 1 , FK 2 , FK 3 are 32 bits each, CK is (CK 0 , CK 1 , . . . , CK 31 ), where CK 0 , CK 1 , . . . , CK 31 are 32 bits each, and the third internal storage space is in the block cipher engine.

17. The processor as claimed in claim 16 , wherein:
the input key sent to the hardware for key extension logic is MK, MK is (MK 0 , MK 1 , MK 2 , MK 3 ), and MK 0 , MK 1 , MK 2 , MK 3 are 32 bits each;
the hardware for key extension logic reads FK and CK from the third internal storage space;
the hardware for key-XOR logic performs following calculations:
(K 0 , K 1 , K 2 , K 3 )=(MK 0 ∧FK 0 , MK 1 ∧FK 1 , MK 2 ∧FK 2 , MK 3 ∧FK 3 )

the hardware for multi-XOR logic performs 32-bit XOR calculations:
(K i+1 ∧K i+2 ∧K i+3 ∧CK i );

the hardware for non-linear transform performs the following calcu

Assignees

• Shanghai Zhaoxin Semiconductor Co Ltd

Inventors

• Huang Zhenhua
• Guan Yingbing
• Li Yanting

Classifications

• H04L9/0866

  involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics · CPC title

• H04L9/0618 Primary

  Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation · CPC title

• H04L9/002

  Countermeasures against attacks on cryptographic mechanisms (network architectures or network communication protocols for protection against malicious traffic H04L63/1441) · CPC title

• H04L2209/80

  Wireless · CPC title

• G06F21/602

  Providing cryptographic facilities or services · CPC title