Display panel, display apparatus, and driving method

Patent metadata

Field	Value
Publication number	US-12154496-B2
Application number	US-202118270850-A
Country	US
Kind code	B2
Filing date	Feb 26, 2021
Priority date	Feb 26, 2021
Publication date	Nov 26, 2024
Grant date	Nov 26, 2024

Abstract

Disclosed are a display panel, a display device and a driving method. The display panel includes a plurality of sub-pixel units located in areas formed by the plurality of scanning signal lines and the plurality of data signal lines, and at least two adjacent sub-pixel units in the first direction and the second direction constitute a pixel island. A plurality of control units each corresponding to a sub-pixel unit row in the pixel island are provided. The control unit includes a control terminal, an input terminal and an output terminal. The control unit is configured to transmit a signal from the input terminal to the output terminal under control of a first signal transmitted by a control signal line corresponding to the control unit, and stop transmitting the signal from the input terminal to the output terminal under control of a second signal transmitted by the control signal line.

First claim

What is claimed is:

1. A display panel, comprising:
a substrate;
a plurality of scanning signal lines on the substrate, wherein the plurality of scanning signal lines extend in a first direction and are arranged in a second direction, and the first direction and the second direction intersect;
a plurality of data signal lines on the substrate, wherein the plurality of data signal lines extend in the second direction and are arranged in the first direction;
a plurality of sub-pixel units located in areas formed by the plurality of scanning signal lines and the plurality of data signal lines respectively, wherein at least two adjacent sub-pixel units in the first direction and the second direction constitute a pixel island;
a plurality of control units located between adjacent pixel islands in the first direction, wherein one pixel island is correspondingly connected with n control units, n represents a quantity of sub-pixel unit rows comprised in the pixel island in the second direction, and one control unit corresponds to one sub-pixel unit row in the pixel island in the first direction; and
a plurality of control signal lines located between the adjacent pixel islands in the first direction respectively, wherein the plurality of control signal lines extend in the second direction and are arranged in the first direction;
wherein:
the sub-pixel unit comprises a first transistor and a drive circuit, a first electrode of the first transistor is connected with a data signal line corresponding to a sub-pixel unit column comprising the sub-pixel unit, a second electrode of the first transistor is connected with the drive circuit in the sub-pixel unit, and a control electrode of the first transistor is connected with control electrodes of first transistors of sub-pixel units located in a same row in the first direction in the pixel island;
the control unit comprises a control terminal, an input terminal and an output terminal, the control terminal of the control unit is connected with a control signal line corresponding to the control unit, the input terminal of the control unit is connected with a scanning signal line corresponding to the control unit, and the output terminal of the control unit is connected with control electrodes of first transistors in a sub-pixel unit row corresponding to the control unit; and
the control unit is configured to transmit a signal from the input terminal to the output terminal under control of a first signal transmitted by the control signal line, and stop transmitting the signal from the input terminal to the output terminal under control of a second signal transmitted by the control signal line.

2. The display panel according to claim 1 , wherein the control unit comprises: a second transistor and a third transistor, and the display panel further comprises:
a plurality of fixed potential signal lines located between adjacent sub-pixel units in the second direction respectively, and the plurality of fixed potential signal lines extend in the first direction and are arranged in the second direction;
a control electrode of the second transistor is connected with the control signal line corresponding to the control unit, a first electrode of the second transistor is connected with the scanning signal line corresponding to the control unit, and a second electrode of the second transistor is connected with control electrodes of first transistors in the sub-pixel unit row corresponding to the control unit;
a control electrode of the third transistor is connected with the control signal line corresponding to the control unit, a first electrode of the third transistor is connected with a fixed potential signal line corresponding to the control unit, and a second electrode of the third transistor is connected with the control electrodes of the first transistors in the sub-pixel unit row corresponding to the control unit;
the second transistor is configured to be turned on under control of the first signal transmitted by the control signal line, and to be turned off under control of the second signal transmitted by the control signal line; and
the third transistor is configured to be turned off under control of the first signal transmitted by the control signal line, and to be turned on under control of the second signal transmitted by the control signal line.

3. The display panel according to claim 2 , wherein the second transistor is an N-type transistor, the third transistor is a P-type transistor, the first signal is a high-level signal, and the second signal is a low-level signal;
or
the second transistor is a P-type transistor, the third transistor is an N-type transistor, the first signal is a low-level signal, and the second signal is a high-level signal.

4. The display panel according to claim 1 , wherein the control unit comprises: a second transistor and a third transistor, the control signal line is a first control signal line, and the display panel further comprises:
a plurality of second control signal lines located between the adjacent pixel islands in the first direction respectively, and the plurality of second control signal lines extend in the second direction and are arranged in the first direction; and
a plurality of fixed potential signal lines located between adjacent sub-pixel units in the second direction respectively, and the plurality of fixed potential signal lines extend in the first direction and are arranged in the second direction; wherein
a control electrode of the second transistor is connected with the first control signal line corresponding to the control unit, a first electrode of the second transistor is connected with the scanning signal line corresponding to the control unit, and a second electrode of the second transistor is connected with control electrodes of first transistors in the sub-pixel unit row corresponding to the control unit;
a control electrode of the third transistor is connected with a second control signal line corresponding to the control unit, a first electrode of the third transistor is connected with a fixed potential signal line corresponding to the control unit, and a second electrode of the third transistor is connected with the control electrodes of the first transistors in the sub-pixel unit row corresponding to the control unit;
the second transistor is configured to be turned on under control of the first signal transmitted by the first control signal line, and to be turned off under control of the second signal transmitted by the first control signal line; and
the third transistor is configured to be turned on under control of a third signal transmitted by the second control signal line, and to be turned off under control of a fourth signal transmitted by the second control signal line.

5. The display panel according to claim 4 , wherein the second transistor is an N-type transistor, the first signal is a high-level signal, and the second signal is a low-level signal; or, the second transistor is a P-type transistor, the first signal is a low-level signal, and the second signal is a high-level signal; and
the third transistor is an N-type transistor, the third signal is a high-level signal, and the fourth signal is a low-level signal; or, the third transistor is a P-type transistor, the third signal is a low-level signal, and the fourth signal is a high-level signal.

6. The display panel according to claim 2 , wherein the first transistor is an N-type transistor, and the fixed potential signal line is configured to transmit the low-level signal;
or
the first transistor is the P-type transistor, and the fixed potential signal line is configured to transmit the high-level signal.

7. The display panel according to claim 1 , wherein the display panel is a liquid crystal

Assignees

• Boe Mled Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Zong Shaolei
• Sun Jigang
• Liu Rui
• Duan Xin
• Sun Wei
• Zhang Junwei
• Wang Hongrun
• Li Fuqiang
• Sun Changfeng
• Zhang Hui
• Dong Xue

Classifications

• G09G2340/0435

  Change or adaptation of the frame rate of the video stream · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0452

  Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components · CPC title

• G09G3/3648

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G09G3/2092

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title