Memory segmentation with substitution

Patent metadata

Field	Value
Publication number	US-12153807-B2
Application number	US-202318161064-A
Country	US
Kind code	B2
Filing date	Jan 29, 2023
Priority date	Jan 29, 2023
Publication date	Nov 26, 2024
Grant date	Nov 26, 2024

Abstract

An apparatus includes a memory, a Memory Section Attribute Storage (MSAS) and a memory access circuit (MAC). The memory includes a plurality of memory sections. The MSAS includes one or more entries, wherein at least some of the entries specify, for respective sections of the memory, respective section security policies, respective section base addresses and respective section sizes. The MAC is configured to receive, from a host, a memory access request that specifies an address to be accessed in the memory, to identify a target memory section that corresponds to the address, responsively to the section base addresses and to the section sizes specified in the MSAS, to receive, from the MSAS, a security policy that corresponds to the target memory section, and to apply the security policy to the memory access request.

First claim

The invention claimed is:

1. An apparatus, comprising:
a memory comprising a plurality of memory sections;
a Memory Section Attribute Storage (MSAS) comprising one or more entries, wherein at least some of the entries specify, for respective sections of the memory, respective section security policies, respective section base addresses and respective section sizes; and
a memory access circuit (MAC), configured to:
receive, from a host, a memory access request that specifies an address to be accessed in the memory;
identify a target memory section that corresponds to the address, responsively to the section base addresses and to the section sizes specified in the MSAS;
receive, from the MSAS, a security policy that corresponds to the target memory section; and
apply the security policy to the memory access request,
wherein the MAC is configured to determine that the address belongs to the target memory section, by identifying that a section-specifying set of bits of the address, a size of the set being derived from a section size in the entry of the of the target memory section, are equal to the corresponding bits of a base address in the entry of the target memory section, and
wherein the MSAS is further configured to perform address remapping between first and second memory sections of a same size, by swapping the section-specifying bits between the entries of the first and second sections.

2. The apparatus according to claim 1 , wherein sizes of the memory sections are integer powers of two, and wherein the base addresses are integer multiples of the respective sizes of the memory sections.

3. The apparatus according to claim 1 , wherein the section-specifying bits are the bits at bit-positions n to N−1, wherein a bit-position 0 is a least-significant bit, 2n is the section size, and 2N is a total size of the memory.

4. A method, comprising:
storing, for a memory comprising a plurality of memory sections, a Memory Section Attribute Storage (MSAS) comprising one or more entries, wherein at least some of the entries specify, for respective sections of the memory, respective section security policies, respective section base addresses and respective section sizes;
receiving, from a host, a memory access request that specifies an address to be accessed in the memory;
identifying a target memory section that corresponds to the address, responsively to the section base addresses and to the section sizes specified in the MSAS;
receiving, from the MSAS, a security policy that corresponds to the target memory section; and
applying the security policy to the memory access request,
wherein identifying the target memory section comprises determining that the address belongs to the target memory section, by identifying that a section-specifying set of bits of the address, a size of the set being derived from a section size in the entry of the of the target memory section, are equal to the corresponding bits of a base address in the entry of the target memory section, and
further comprising performing address remapping between first and second memory sections of a same size, by swapping the section-specifying bits between the entries of the first and second sections.

5. The method according to claim 4 , wherein sizes of the memory sections are integer powers of two, and wherein the base addresses are integer multiples of the respective sizes of the memory sections.

6. The method according to claim 4 , wherein the section-specifying bits are the bits at bit-positions n to N−1, wherein a bit-position 0 is a least-significant bit, 2n is the section size, and 2N is a total size of the memory.

Assignees

• Winbond Electronics Corp

Inventors

• Kaluzhny Uri
• Tasher Nir
• Admon Itay
• Luko Mark

Classifications

• G06F12/1475

  in a virtual system, e.g. with translation means · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0637

  Permissions · CPC title

• G06F2212/1052

  Security improvement · CPC title