Array substrate, display panel and display apparatus

Patent metadata

Field	Value
Publication number	US-12150343-B2
Application number	US-202117382549-A
Country	US
Kind code	B2
Filing date	Jul 22, 2021
Priority date	Jul 3, 2019
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

An array substrate, a display panel and a display apparatus are provided. An array substrate includes: a first display region including M display sub-regions arranged in an array, each display sub-region including first pixel units arranged in an array, and each first pixel unit including first pixels with N colors, where M is a natural number greater than 1 and N is a natural number; and a second display region adjacent to the first display region and having a light transmittance less than that of the first display region, where the first pixels with a same color in a same display sub-region are connected to a common first pixel circuit located in the second display region; and first pixel circuits for the first pixels with a same color in two display sub-regions adjacent to a central axis of the first display region are symmetrical with respect to the central axis.

First claim

The invention claimed is:

1. An array substrate, comprising:
a first display region comprising M display sub-regions arranged in array, wherein each display sub-region of the display sub-regions comprises first pixel units arranged in the array, each first pixel unit of the first pixel units comprises first pixels with N colors, M is a natural number greater than 1, and N is a natural number; and
a second display region adjacent to the first display region and having a light transmittance less than a light transmittance of the first display region, wherein the second display region comprises a first sub-display region and a second sub-display region, the first sub-display region is located between the first display region and the second sub-display region, the first sub-display region comprises second pixel units arranged in the array, the second sub-display region comprises third pixel units arranged in the array, each of the second pixel units comprises second pixels with N colors, each of the third pixel units comprises third pixels with N colors,
in a column direction of the third pixel units, a first central axis of an m-th column of the third pixel units and an (m+1)-th column of the third pixel units in the second sub-display region substantially coincides with a second central axis of an n-th column of the second pixel units in the first sub-display region, m and n are respectively natural numbers, wherein the third pixel unit, at the m-th column and the (m+1)-th column, do not overlap the first central axis,
in a column direction of the third pixel units, a third central axis of a k-th column of the third pixel units and a (k+1)-th column of the third pixel units in the second sub-display region coincides with a fourth central axis of a j-th column of the display sub-regions in the first display region, j and k are respectively natural numbers, wherein the third pixel unit, at the j-th column and the (i+1)-th column, do not overlap the third central axis.

2. The array substrate according to claim 1 , wherein two first pixel circuits for the first pixels with the same color in two of the display sub-regions symmetrical with respect to the central axis of the first display region are symmetrical with respect to the central axis.

3. The array substrate according to claim 1 , wherein M is 8 and the array of the display sub-regions has one row and eight columns, four columns of the display sub-regions in the eight columns are located on a first side of the central axis, the other four columns of the display sub-regions are located on a second side of the central axis, and the first side and the second side are symmetrical with respect to the central axis.

4. The array substrate according to claim 1 , wherein the third pixel units in the second sub-display region has a density greater than that of the second pixel units in the first sub-display region.

5. The array substrate according to claim 1 , wherein the first sub-display region further comprises second pixel circuits arranged in the array and connected with the second pixels, the second sub-display region comprises a plurality of third pixel circuits arranged in the array and connected with the third pixels,
for a same color, a second pixel circuit for the second pixels in the n-th column of the second pixel units and a third pixel circuit for the third pixels in the m-th column of the third pixel units are connected to a common data line, and the m-th column of the third pixel units are closer to the first sub-display region than the (m+1)-th column of the third pixel units, or the second pixel circuit for the second pixels in the n-th column of the second pixel units and a third pixel circuit for the third pixels in the (m+1)-th column of the third pixel units are connected to a common data line, and the (m+1)-th column of the third pixel units are closer to the first sub-display region than the m-th column of the third pixel units.

6. The array substrate according to claim 1 , wherein the second sub-display region comprises a plurality of third pixel circuits arranged in the array and connected with the third pixels, the first pixels with a same color in a same display sub-region are connected to a common first pixel circuit which is located in the second display region,
for a same color, the first pixel circuit for the first pixels in the j-th column of the display sub-regions and a third pixel circuit for the third pixels in the k-th column of the third pixel units are connected to a common data line, and the k-th column of the third pixel units are closer to the first sub-display region than the (k+1)-th column of the third pixel units, or the first pixel circuit for the first pixels in the j-th column of the display sub-regions and a third pixel circuit for the third pixels in the (k+1)-th column of the third pixel units are connected to a common data line, and the (k+1)-th column of the third pixel units are closer to the first sub-display region than the k-th column of the third pixel units.

7. The array substrate according to claim 1 , wherein the first sub-display region further comprises second pixel circuits arranged in the array, the second pixels are connected with the second pixel circuits in a one-to-one correspondence, and the second pixel circuits are symmetrical with respect to the central axis.

8. The array substrate according to claim 7 , wherein the second sub-display region comprises a plurality of third pixel circuits arranged in the array and the third pixels are connected with the third pixel circuits in a one-to-one correspondence.

9. The array substrate according to claim 8 , further comprising:
a plurality of first pixel circuits connected to the first pixels, wherein each of the third pixel circuits is a seven transistors and one capacitor pixel circuit, each of the second pixel circuits is a seven transistors and one capacitor pixel circuit, and each of the first pixel circuits is a one transistor pixel circuit, a two transistors and one capacitor pixel circuit, a three transistors and one capacitor pixel circuit, or a seven transistors and one capacitor pixel circuit.

10. The array substrate according to claim 1 , further comprising:
a plurality of first pixel circuits connected to the first pixels, wherein the plurality of first pixel circuits is located in an area of the first sub-display region close to the first display region.

11. The array substrate according to claim 1 , wherein the first pixel units in the first display region have a density less than a density of the third pixel units in the second sub-display region, and a light transmittance of the first display region is greater than a light transmittance of the second sub-display region.

12. The array substrate according to claim 1 , wherein the second pixel units in the first sub-display region have a same density as a density of the first pixel units in the first display region.

13. The array substrate according to claim 1 , wherein the third pixel units in the second sub-display region have a density double that of a density of the second pixel units in the first sub-display region.

14. The array substrate according to claim 1 , wherein each of the first pixels has a same opening area as each of the second pixels; and the opening area of each of the first pixels is 4 times an opening area of each of the third pixels.

15. The array substrate according to claim 1 , wherein the first display region is drop-shaped, circular, rectangular, elliptical, diamond-shaped, semi-circular or semi-elliptical.

16. The array substrate according to claim 1 , wherein

Assignees

• Kunshan Govisionox Optoelectronics Co Ltd

Inventors

• Chang Miao
• Zhang Lu
• Hu Siming
• Han Zhenzhen

Classifications

• H10K59/87

  Passivation; Containers; Encapsulations · CPC title

• H10K59/1213 Primary

  the pixel elements being TFTs · CPC title

• H10K59/60 Primary

  OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G3/3208

  organic, e.g. using organic light-emitting diodes [OLED] · CPC title