Array of capacitors, array of memory cells, methods of forming an array of capacitors, and methods of forming an array of memory cells

Patent metadata

Field	Value
Publication number	US-12150312-B2
Application number	US-202217567268-A
Country	US
Kind code	B2
Filing date	Jan 3, 2022
Priority date	Dec 19, 2018
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

A method of forming an array of capacitors comprises forming a plurality of horizontally-spaced groups that individually comprise a plurality of horizontally-spaced lower capacitor electrodes having a capacitor insulator thereover. Adjacent of the groups are horizontally spaced farther apart than are adjacent of the lower capacitor electrodes within the groups. A void space is between the adjacent groups. An upper capacitor electrode material is formed in the void space and in the groups over the capacitor insulator and the lower capacitor electrodes. The upper capacitor electrode material in the void space connects the upper capacitor electrode material that is in the adjacent groups relative to one another. The upper capacitor electrode material less-than-fills the void space. At least a portion of the upper capacitor electrode material is removed from the void space to disconnect the upper capacitor electrode material in the adjacent groups from being connected relative to one another. A horizontally-elongated conductive line is formed atop and is directly electrically coupled to the upper capacitor electrode material in individual of the groups. Other methods, including structure independent of method of manufacture, are disclosed.

First claim

The invention claimed is:

1. An array of capacitors comprising:
a plurality of horizontally-spaced groups individually comprising horizontally-spaced lower capacitor electrodes, individual of the groups comprising rows and columns of the horizontally-spaced lower capacitor electrodes, the rows and the columns each comprising a plurality of the horizontally-spaced lower capacitor electrodes, adjacent of the groups being horizontally spaced farther apart than are adjacent of the lower capacitor electrodes within the groups;
a capacitor insulator over the lower capacitor electrodes;
an upper capacitor electrode that is common to all capacitors in the individual groups; the capacitors in the individual groups individually comprising one of the lower capacitor electrodes, the capacitor insulator, and the common upper capacitor electrode in the respective individual group; and
a horizontally-elongated conductive line atop and directly electrically coupled to the upper capacitor electrode in the individual groups, the horizontally-elongated conductive line horizontally spanning across multiple of the rows and multiple of the columns.

2. The array of capacitors of claim 1 further comprising an array of transistors below the array of capacitors, the transistors individually being directly electrically coupled to individual of the lower capacitor electrodes.

3. The array of capacitors of claim 2 wherein the transistors are vertical transistors.

4. The array of capacitors of claim 2 comprising an array of memory cells individually comprising one of the capacitors and one of the transistors.

5. The array of capacitors of claim 1 comprising a plurality of horizontally-spaced bracing structures, adjacent of the bracing structures being horizontally spaced farther apart than are adjacent of the lower capacitor electrodes within the groups.

6. The array of capacitors of claim 5 comprising a plurality of openings formed through individual of the bracing structures.

7. The array of capacitors of claim 6 wherein the capacitor insulator extends through individual of the openings.

8. The array of capacitors of claim 6 wherein the common upper capacitor electrode extends through individual of the openings.

9. The array of capacitors of claim 6 wherein the capacitor insulator and the common upper capacitor electrode extend through individual of the openings.

10. The array of capacitors of claim 6 wherein individual of the openings are circumferentially surrounded by multiple of the lower capacitor electrodes.

11. The array of capacitors of claim 10 wherein the multiple is four per the individual openings.

12. The array of capacitors of claim 11 wherein the four are equally circumferentially spaced relative one another circumferentially around the individual openings.

13. The array of capacitors of claim 1 comprising a plurality of horizontally-spaced bracing structures, the horizontally-elongated conductive lines individually having opposing lateral edges in a vertical cross-section that are laterally outward of opposing lateral edges of individual of the bracing structures in the vertical cross-section.

14. The array of capacitors of claim 1 comprising a plurality of horizontally-spaced bracing structures, the horizontally-elongated conductive lines individually having opposing lateral edges in a vertical cross-section that are laterally outward of opposing lateral edges of the common upper capacitor electrode in the respective individual group.

15. The array of capacitors of claim 1 comprising:
a plurality of horizontally-spaced bracing structures, the horizontally-elongated conductive lines individually having opposing lateral edges in a vertical cross-section that are laterally outward of opposing lateral edges of individual of the bracing structures in the vertical cross-section; and
the opposing lateral edges the horizontally-elongated conductive lines in the vertical cross-section being laterally outward of opposing lateral edges of the common upper capacitor electrode in the respective individual group.

16. An array of ferroelectric memory cells individually comprising a ferroelectric capacitor above a transistor, comprising:
rows and columns of vertical transistors, an access line interconnecting multiple of the transistors along individual of the rows of the vertical transistors in a row direction, a digitline interconnecting multiple of the transistors along individual of the columns of the vertical transistors in a column direction, the transistors individually comprising a lower source/drain region directly electrically coupled with individual of the digitlines, the transistors individually comprising an upper source/drain region;
a plurality of horizontally-spaced groups individually comprising horizontally-spaced lower capacitor electrodes, individual of the lower capacitor electrodes being directly above and directly electrically coupled to individual of the upper source/drain regions, individual of the groups comprising lower-capacitor-electrode rows and lower-capacitor-electrode columns of the horizontally-spaced lower capacitor electrodes, the lower-capacitor-electrode rows and the lower-capacitor-electrode columns each comprising a plurality of the horizontally-spaced lower capacitor electrodes, adjacent of the groups being horizontally spaced apart from one another by a gap that is greater than horizontal spacing between adjacent of the lower capacitor electrodes within the groups, the gap being horizontally elongated in the column direction;
a ferroelectric capacitor insulator over the lower capacitor electrodes;
an upper capacitor electrode that is common to all capacitors in the individual groups; the capacitors in the individual groups individually comprising one of the lower capacitor electrodes, the capacitor insulator, and the common upper capacitor electrode in the respective individual group; and
a horizontally-elongated conductive line atop and directly electrically coupled to the upper capacitor electrode in the individual groups, the horizontally-elongated conductive line horizontally spanning across multiple of the lower-capacitor-electrode rows and multiple of the lower-capacitor-electrode columns.

17. The array of capacitors of claim 16 comprising a plurality of horizontally-spaced bracing structures, the horizontally-elongated conductive lines individually having opposing lateral edges in a vertical cross-section that are laterally outward of opposing lateral edges of individual of the bracing structures in the vertical cross-section.

18. The array of capacitors of claim 16 comprising a plurality of horizontally-spaced bracing structures, the horizontally-elongated conductive lines individually having opposing lateral edges in a vertical cross-section that are laterally outward of opposing lateral edges of the common upper capacitor electrode in the respective individual group.

19. The array of capacitors of claim 16 comprising:
a plurality of horizontally-spaced bracing structures, the horizontally-elongated conductive lines individually having opposing lateral edges in a vertical cross-section that are laterally outward of opposing lateral edges of individual of the bracing structures in the vertical cross-section; and
the opposing lateral edges the horizontally-elongated conductive lines in the vertical cross-section being laterally outward of opposing lateral edges of the common upper capacitor electrode in the respective individual group.

20. The array of capacitors of claim 16

Assignees

• Micron Technology Inc

Inventors

• Chhajed Sameer
• Chavan Ashonita A
• Fischer Mark
• Ramaswamy Durai Vishak Nirmal

Classifications

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D30/025

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H10D1/692 Primary

  Electrodes · CPC title

• H10D1/042

  using deposition processes to form electrode extensions · CPC title