Microelectronic devices and memory devices

Patent metadata

Field	Value
Publication number	US-12150289-B2
Application number	US-202117203236-A
Country	US
Kind code	B2
Filing date	Mar 16, 2021
Priority date	Aug 19, 2019
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

A method of forming a microelectronic device comprises forming a spacer structure having a rectangular ring horizontal cross-sectional shape over a transistor, a portion of the spacer structure horizontally overlapping a drain region of the transistor. A masking structure is formed over the spacer structure and the transistor, the masking structure exhibiting an opening therein horizontally overlapping the drain region of the transistor and the portion of the spacer structure. A portion of an isolation structure overlying the drain region of the transistor is removed using the masking structure and the portion of the spacer structure as etching masks to form a trench vertically extending through the isolation structure to the drain region of the transistor. A drain contact structure is formed within the trench in the isolation structure. Microelectronic devices, memory devices, and electronic systems are also described.

First claim

What is claimed is:

1. A microelectronic device, comprising:
a transistor comprising:
a gate structure;
sidewall spacer structures comprising a single dielectric material directly abutting outer sidewalls of the gate structure;
a dielectric cap structure vertically overlying the gate structure, the dielectric cap structure comprising a single additional dielectric material directly abutting inner surfaces of the sidewall spacer structures and confined within horizontal boundaries of the gate structure;
a source region horizontally neighboring a first side of the gate structure;
a drain region horizontally neighboring a second side of the gate structure opposing the first side of the gate structure, the drain region and the source region having substantially equal horizontal areas relative to one another; and
a channel region vertically underlying the gate structure and horizontally intervening between the source region and the drain region;

a shallow trench isolation (STI) structure horizontally neighboring the drain region of the transistor and an additional drain region;
an isolation structure comprising dielectric material overlying the STI structure and portions of the drain region and the additional drain region;
a source contact structure horizontally neighboring the first side of the gate structure of the transistor and in contact with the source region of the transistor, a horizontal center of the source contact structure substantially aligned with a horizontal center of the source region in each of a first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction; and
a drain contact structure horizontally neighboring the second side of the gate structure of the transistor and in contact with the drain region of the transistor,
a horizontal center of the drain contact structure substantially aligned with a horizontal center of the drain region in each of the first horizontal direction and the second horizontal direction,
the drain contact structure substantially aligned with the source contact structure in the first horizontal direction, having a greater length than the source contact structure in the first horizontal direction, and having substantially the same width as the source contact structure in the second horizontal direction, and
upper surfaces of each of the source contact structure and the drain contact structure substantially coplanar with an upper surface of the dielectric cap structure, an upper surface of the isolation structure, and upper surfaces of the sidewall spacer structures.

2. The microelectronic device of claim 1 , further comprising another transistor horizontally neighboring the transistor and comprising:
another gate structure;
the source region horizontally neighboring a first side of the another gate structure, the source region shared between the transistor and the another transistor;
another drain region horizontally neighboring a second side of the another gate structure opposing the first side of the another gate structure; and
another channel region vertically underlying the another gate structure and horizontally intervening between the source region and the another drain region; and

another drain contact structure horizontally neighboring the second side of the another gate structure of the another transistor and in contact with the another drain region of the another transistor, the another drain contact structure substantially aligned with the source contact structure and the drain contact structure in the first horizontal direction and exhibiting substantially the same horizontal area as the drain contact structure.

3. The microelectronic device of claim 1 , further comprising:
another transistor horizontally neighboring the transistor and comprising:
another gate structure;
another source region horizontally neighboring a first side of the another gate structure;
the additional drain region horizontally neighboring a second side of the another gate structure opposing the first side of the another gate structure, the additional drain region of the another transistor horizontally neighboring the drain region of the transistor; and
another channel region vertically underlying the another gate structure and horizontally intervening between the another source region and the additional drain region;

another source contact structure horizontally neighboring the first side of the another gate structure of the another transistor and in contact with the another source region of the another transistor; and
another drain contact structure horizontally neighboring the second side of the another gate structure of the another transistor and in contact with the additional drain region of the another transistor, the another drain contact structure substantially horizontally aligned with the drain contact structure in the first horizontal direction and exhibiting substantially the same horizontal area as the drain contact structure.

4. A memory device, comprising:
memory cells operably coupled to digit lines and word lines; and
a memory controller operably coupled to the memory cells and comprising a sense device comprising:
a transistor;
a source contact structure in contact with a source region of the transistor, the source contact structure substantially horizontally centered about the source region in each of a first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction;
a drain contact structure in contact with a drain region of the transistor having substantially the same horizontal area as the source region, the drain contact structure substantially horizontally centered about the drain region in each of the first horizontal direction and the second horizontal direction, and comprising:
a length in the first horizontal direction greater than a length of the source contact structure in the first horizontal direction; and
a width in the second horizontal direction substantially equal to a width of the source contact structure in the second horizontal direction;

a dielectric isolation structure abutting sidewalls of the drain contact structure;
a shallow trench isolation (STI) structure underlying the dielectric isolation structure and horizontally interposed between the drain region and an additional drain region;
a gate structure horizontally interposed between the source contact structure and the drain contact structure in the second horizontal direction, a distance from the gate structure of the transistor in the second horizontal direction substantially equal to an additional distance from the gate structure of the transistor to the source contact structure in the second horizontal direction;
dielectric spacer structures comprising a single dielectric material horizontally interposed directly between the gate structure and each of the source contact structure and the drain contact structure in the second horizontal direction; and
a dielectric cap structure comprising a single additional dielectric material vertically overlying and confined within horizontal boundaries of the gate structure, the dielectric cap structure having an upper surface substantially coplanar with upper surfaces of the dielectric spacer structures, the dielectric isolation structure, the source contact structure, and the drain contact structure.

5. The memory device of claim 4 , wherein the transistor of the memory controller comprises a channel region horizontally intervening between the source region and the drain region in the second horizontal direction, wherein the gate structure is confined within vertical boundaries of the source contact structure and the drain contact structure.

6. The memory device of claim 4 , further comprising a gate die

Assignees

• Micron Technology Inc

Inventors

• Lee Si-Woo
• Lee Kyuseok
• Hwang Sangmin

Classifications

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/069 Primary

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10D84/80

  characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs (H10D84/40 takes precedence) · CPC title