Isolator with forward and return paths

Patent metadata

Field	Value
Publication number	US-12149389-B2
Application number	US-202318155999-A
Country	US
Kind code	B2
Filing date	Jan 18, 2023
Priority date	Jan 18, 2023
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

Systems, devices, and methods for isolating digital signals are described. A carrier signal can be modulated using a first signal to generate a first modulated signal. The carrier signal and the first modulated signal can be transmitted through a forward path in an isolation barrier, where transmitting the carrier signal through the isolation barrier can transform the carrier signal into a delayed carrier signal. The first modulated signal can be demodulated to recover the first signal. The delayed carrier signal can be modulated using a second signal to generate a second modulated signal. The delayed carrier signal and the second modulated signal can be transmitted through a return path in the isolation barrier, where the return path and the forward path has opposite directions.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first chip;
a second chip;
an isolation barrier;
the first chip being configured to:
receive a first signal from a first device connected to the first chip, wherein the first signal is designated for a second device;
modulate a carrier signal, using the first signal, to generate a first modulated signal; and
transmit the carrier signal and the first modulated signal to the second chip through the isolation barrier; and

the second chip being configured to:
receive the carrier signal and the first modulated signal, wherein the carrier signal is received as a delayed carrier signal;
demodulate the first modulated signal to recover the first signal;
modulate the delayed carrier signal, using a second signal designated for the first device, to generate a second modulated signal; and
transmit the delayed carrier signal and the second modulated signal to the first chip through the isolation barrier.

2. The semiconductor device of claim 1 , wherein:
the isolation barrier includes a first isolation component, a second isolation component, a third isolation component, and a fourth isolation component;
the first chip is configured to transmit the carrier signal to the second chip through the first isolation component;
the first chip is configured to transmit the first modulated signal to the second chip through the second isolation component;
the second chip is configured to transmit the delayed carrier signal to the first chip through the third isolation component; and
the second chip is configured to transmit the second modulated signal to the first chip through the fourth isolation component.

3. The semiconductor device of claim 2 , wherein each one of the first isolation component, the second isolation component, the third isolation component and the fourth isolation component is one of a capacitor and a transformer.

4. The semiconductor device of claim 2 , wherein:
the first chip includes N digital signal modulators;
the first isolation component and the second isolation component are among N isolation components that transfers signals from the first chip to the second chip;
the second chip includes M digital signal modulators; and
the third isolation component and the fourth isolation component are among M isolation components that transfers signals from the second chip to the first chip.

5. The semiconductor device of claim 1 , wherein:
the first chip includes:
N digital signal modulators; and
M digital signal demodulators;

the second chip includes:
N digital signal demodulators; and
M digital signal modulators;

the first chip is configured to distribute the carrier signal to the N digital signal modulators in the first chip;
the second chip is configured to distribute the delayed carrier signal to the M digital signal modulators in the second chip; and
the second chip is configured to transmit the delayed carrier signal to the M digital signal demodulators in the first chip.

6. The semiconductor device of claim 1 , wherein the carrier signal is a spread spectrum signal generated by a voltage controlled oscillator.

7. The semiconductor device of claim 1 , wherein:
the isolation barrier applies a delay to the carrier signal to transform the carrier signal into the delayed carrier signal;
the isolation barrier applies the delay to the delayed carrier signal to transform the delayed carrier signal into a twice delayed carrier signal; and
the first chip is configured to:
receive the twice delayed carrier signal; and
demodulate the twice delayed carrier signal to recover the second signal.

8. The semiconductor device of claim 1 , further comprising:
a third chip; and
the second chip is further configured to:
receive a third signal designated for the third chip;
modulate the delayed carrier signal using the third signal to generate a third modulated signal; and
transmit the delayed carrier signal and the third modulated signal to the third chip through the isolation barrier.

9. A method for transmitting a signal, the method comprising:
receiving a first signal from a first device, wherein the first signal is designated for a device;
modulating a carrier signal using the first signal to generate a first modulated signal;
transmitting the carrier signal and the first modulated signal through a forward path in an isolation barrier, wherein transmitting the carrier signal through the isolation barrier transforms the carrier signal into a delayed carrier signal;
demodulating the first modulated signal to recover the first signal;
modulating the delayed carrier signal using a second signal designated for another device to generate a second modulated signal; and
transmitting the delayed carrier signal and the second modulated signal through a return path in the isolation barrier, wherein the return path and the forward path has opposite directions.

10. The method of claim 9 , wherein:
transmitting the carrier signal through the forward path comprises transmitting the carrier signal through a first isolation component of the isolation barrier;
transmitting the first modulated signal through the forward path comprises transmitting the first modulated signal through a second isolation component of the isolation barrier;
transmitting the delayed carrier signal through the return path comprises transmitting the delayed carrier signal through a third isolation component of the isolation barrier; and
transmitting the second modulated signal through the return path comprises transmitting the second modulated signal through a fourth isolation component of the isolation barrier.

11. The method of claim 10 , wherein each one of the first isolation component, the second isolation component, the third isolation component and the fourth isolation component is one of a capacitor and a transformer.

12. The method of claim 9 , further comprising operating a voltage controlled oscillator to generate the carrier signal.

13. The method of claim 9 , wherein:
transmitting the carrier signal through the forward path comprises applying a delay to the carrier signal to transform the carrier signal into the delayed carrier signal;
transmitting the delayed carrier signal through the return path comprises applying the delay to the delayed carrier signal to transform the delayed carrier signal into a twice delayed carrier signal; and
the method further comprising demodulating the twice delayed carrier signal to recover the second signal.

14. A semiconductor device comprising:
a first device;
a second device; and
an isolator including:
a first chip;
a second chip;
an isolation barrier;
the first chip being configured to:
receive a first signal from the first device, wherein the first signal is designated for the second device;
modulate a carrier signal using the first signal to generate a first modulated signal; and
transmit the carrier signal and the first modulated signal to the second chip through the isolation barrier;

the second chip being configured to:
receive the carrier signal and the first modulated signal, wherein the carrier signal is received as a delayed carrier signal;
demodulate the first modulated signal to recover the first signal;
receive a second signal from the second device, wherein the second signal is designated for the first device;
modulate the delayed carrier signal using the second signal to generate a second modulated signal; and
transmit the delayed carrier signal and the second modulated signal to the first chip through the isolation barrier; and

the first chip is further c

Assignees

• Renesas Electronics America Inc

Inventors

• Sato Tetsuo
• Chen Jiang
• Sha Qiu

Classifications

• H10W44/206

  Wires · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H04L25/0266

  Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling · CPC title

• H03C3/0908

  using a phase locked loop · CPC title

• H04L27/06 Primary

  Demodulator circuits; Receiver circuits · CPC title