Data acquisition method, apparatus and device, and storage medium

Patent metadata

Field	Value
Publication number	US-12149270-B2
Application number	US-202017781087-A
Country	US
Kind code	B2
Filing date	Nov 26, 2020
Priority date	Dec 9, 2019
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

The present application provides a data acquisition method, a data acquisition apparatus, a data acquisition device and a storage medium. The data acquisition method includes: obtaining a first storage flag for indicating a flag bit at which first data starts to be acquired and stored; when a first data acquisition clock is asynchronous with a second data acquisition clock, obtaining a second storage flag being a storage flag bit corresponding to the first storage flag after the first storage flag crosses from the first data acquisition cock to the second data acquisition clock, according to the first data acquisition clock and the second data acquisition clock; and performing anti-jitter processing on the second storage flag to obtain a third storage flag, and acquiring second data according to the third storage flag, a delay between the first data and the second data acquired each time is kept unchanged.

First claim

What is claimed is:

1. A data acquisition method, comprising:
obtaining a first storage flag, the first storage flag is configured to indicate a flag bit at which first data starts to be acquired and stored;
in response to a first data acquisition clock and a second data acquisition clock asynchronous with each other, obtaining a second storage flag according to the first data acquisition clock and the second data acquisition clock, the second storage flag is a storage flag bit corresponding to the first storage flag after the first storage flag crosses from the first data acquisition clock to the second data acquisition clock; and
performing anti-jitter processing on the second storage flag to obtain a third storage flag, and acquiring second data according to the third storage flag, wherein, a delay between the first data and the second data acquired each time is kept unchanged,
a length of the delay is related to a link delay from a digital pre-distortion circuit to a power amplifier.

2. The method of claim 1 , further comprising:
before obtaining the first storage flag, acquiring a first sampling rate corresponding to the first data and a second sampling rate corresponding to the second data; and
configuring a first counting period of a first counter and a count value in the first counting period, and a second counting period of a second counter and a count value in the second counting period according to the first sampling rate and the second sampling rate, wherein lengths of time durations corresponding to the first counting period and the second counting period are equal.

3. The method of claim 2 , wherein the performing anti-jitter processing on the second storage flag to obtain a third storage flag comprises:
in response to that the second storage flag corresponds to a count value within a preset jitter range of the second counter, adjusting the second storage flag to a position corresponding to any count value outside the jitter range in the second counting period for obtaining the third storage flag.

4. The method of claim 2 , wherein the performing anti-jitter processing on the second storage flag to obtain a third storage flag comprises:
in response to that the second storage flag corresponds to a first count value outside the preset jitter range of the second counter, modifying the first count value corresponding to the second storage flag to a second count value, wherein the second count value is any count value within the jitter range; and
recounting the second counter by taking the second count value as a starting point for counting, adjusting the second storage flag to a position corresponding to a third count value to obtain the third storage flag, wherein the third count value is any count value outside the jitter range in the second counting period after the recounting.

5. The method of claim 1 , further comprising:
after obtaining the first storage flag, performing delay processing on the first storage flag, so that the first storage flag is delayed for a time duration relating to the link delay from the digital pre-distortion circuit to the power amplifier.

6. The method of claim 5 , further comprising:
in response to a first data acquisition clock and a second data acquisition clock synchronous with each other, acquiring the second data according to the first storage flag subjected to the delay processing.

7. The method of claim 1 , wherein, in response to that a current type of data acquisition is configured to be digital pre-distortion data acquisition, the first data are downlink data and the second data are feedback data.

8. The method of claim 1 , wherein, in response to that a current type of data acquisition is configured to be data acquisition for detecting a standing wave ratio, during acquisition of downlink data and feedback data, the first data are the downlink data and the second data are the feedback data; and during acquisition of downlink data and reflection data, the first data are the downlink data and the second data are the reflection data.

9. A data acquisition device, comprising a memory and a processor, the memory stores a computer program, the processor, when executes the computer program, performs the method of claim 1 .

10. A non-transitory storage medium having a computer program stored thereon, the computer program, when executed by a processor, performs the method of claim 1 .

11. A data acquisition apparatus, comprising:
a first obtaining module configured to obtain a first storage flag, the first storage flag is configured to indicate a flag bit at which first data starts to be acquired and stored;
a second obtaining module configured to, in response to that a first data acquisition clock is asynchronous with a second data acquisition clock, obtain a second storage flag according to the first data acquisition clock and the second data acquisition clock, the second storage flag is a storage flag bit corresponding to the first storage flag after the first storage flag crosses from the first data acquisition clock to the second data acquisition clock;
an anti-jitter processing module configured to perform anti-jitter processing on the second storage flag to obtain a third storage flag; and
a first acquisition module configured to acquire a second data according to the third storage flag, wherein, a delay between the first data and the second data acquired each time is kept unchanged,
wherein, a length of the delay is related to a link delay from a digital pre-distortion circuit to a power amplifier.

12. A data acquisition method, comprising:
obtaining a first storage flag, the first storage flag is configured to indicate a flag bit at which first data starts to be acquired and stored;
in response to a first data acquisition clock and a second data acquisition clock asynchronous with each other, obtaining a second storage flag according to the first data acquisition clock and the second data acquisition clock, the second storage flag is a storage flag bit corresponding to the first storage flag after the first storage flag crosses from the first data acquisition clock to the second data acquisition clock, and
performing anti-jitter processing on the second storage flag to obtain a third storage flag, and acquiring second data according to the third storage flag, wherein, a delay between the first data and the second data acquired each time is kept unchanged,
wherein in response to that a type of each data acquisition is configured to be digital pre-distortion data acquisition, the first data are downlink data and the second data are feedback data,
in response to that the type of each data acquisition is configured to be data acquisition for detecting a standing wave ratio, during acquisition of downlink data and feedback data, the first data are the downlink data and the second data are the feedback data; and during acquisition of downlink data and reflection data, the first data are the downlink data and the second data are the reflection data.

Assignees

• Zte Corp
• Sanechips Tech Co Ltd

Inventors

• Du Jinzhou
• Gong Xiaoliang
• Hu Anwen
• Wen Long

Classifications

• H04B2001/0425

  with linearisation using predistortion · CPC title

• H03F1/32

  Modifications of amplifiers to reduce non-linear distortion (by negative feedback H03F1/34) · CPC title

• H04B2001/0433

  with linearisation using feedback · CPC title

• H04L25/49

  using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels {; Baseband coding techniques specific to data transmission systems (spectral shaping H04L25/03828)} · CPC title

• H04B1/04

  Circuits · CPC title