Low-noise millimeter-wave fractional-N frequency synthesizer

Patent metadata

Field	Value
Publication number	US-12149254-B2
Application number	US-202318321017-A
Country	US
Kind code	B2
Filing date	May 22, 2023
Priority date	May 27, 2022
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

The disclosure relates to mixed analog-digital circuits, and more specifically a low-noise millimeter-wave fractional-N frequency synthesizer. It overcomes quantization noise and fractional spurs caused by the limited dynamic range and nonlinearity of time error amplifiers (TA) in traditional phase-locked loop structures based on TA. In addition to the traditional structure, the synthesizer includes a coarse digital-to-time converter (CDTC), a fine digital-to-time converter (FDTC), and DTC non-linearity calibration circuits. By inserting the CDTC and FDTC before and after the TA, respectively, the variance of the input phase difference of the TA can be reduced, thereby improving the TA linearity and suppressing the quantization noise and spur generated by fractional-N operation. Furthermore, by using non-linearity calibration, the non-linearity of DTC and TA can be compensated to avoid large quantization noise and spur while the second order quantization noise reshaping is maintained. Furthermore, a high-gain TA can increase the resolution of the FDTC.

First claim

What is claimed:

1. A low-noise millimeter-wave fractional-N frequency synthesizer, comprising a phase-frequency detector (PFD), a time amplifier (TA), a charge pump (CP), a loop filter (LF), a voltage-controlled oscillator (VCO), a divider and a delta-sigma modulator (DSM), a coarse digital-to-time convertor (CDTC), a fine digital-to-time convertor (FDTC) and two digital non-linearity calibration circuits, wherein:
an input of the CDTC is connected to an output of the divider and an output of CDTC is connected to an input of the PFD, an input of the FDTC is connected to an output of the TA and an output of the FDTC is connected to an input of the CP, the digital non-linearity calibration circuits comprise a first non-linearity calibration module, a second non-linearity calibration module and a bang-bang phase detector (BBPD), an output signal of the PFD is connected to an input of the bang-bang phase detector, and the bang-bang phase detector extracts phase error information and connects it to each of the two digital non-linearity calibration circuits, the first non-linearity calibration module generates a first control code for the CDTC and is connected to a control terminal of the CDTC, and the second non-linearity calibration module generates a second control code for the FDTC and is connected to a control terminal of the FDTC.

2. The low-noise millimeter-wave fractional-N frequency synthesizer according to claim 1 , wherein an input signal f in is connected to a crystal oscillator signal input of the FDTC, an output signal φ pfd of the PFD is connected to an input of the TA to generate an output signal φ ta , the output signal φ ta is connected to the input of the FDTC, which generates an output signal φ fdtc and is connected to the input of the CP.

3. The low-noise millimeter-wave fractional-N frequency synthesizer according to claim 2 , wherein the CP generates an output current signal and converts it to a voltage signal V tune by the loop filter, and the voltage signal V tune is connected to a control terminal of the VCO, the VCO generates an output signal f out .

4. The low-noise millimeter-wave fractional-N frequency synthesizer according to claim 2 , wherein the output signal f out is fed back to an input of the divider, the divider generates a divided frequency signal f div that is connected to the input of the CDTC and serves as a clock for digital circuits, and the DSM generates a corresponding phase residual information φ dsm and a control signal N div , which are connected to a phase residual input of the first non-linearity calibration module and a control terminal of the divider, respectively.

5. The low-noise millimeter-wave fractional-N frequency synthesizer according to claim 1 , wherein the first non-linearity calibration module comprises: a first DTC compensation module and a first DTC calibration module.

6. The low-noise millimeter-wave fractional-N frequency synthesizer according to claim 5 , wherein the first DTC compensation module comprises: a first lookup table, a first threshold calculation module, a first arrayed comparator and a first encoder.

7. The low-noise millimeter-wave fractional-N frequency synthesizer according to claim 6 , wherein the first lookup table stores delay data for each control word of the corresponding CDTC, the threshold calculation module calculates the average value of each adjacent delay data in the first lookup table and outputs the calculation result as thresholds, and the first arrayed comparator compares a search threshold with the phase residue input φ dsm from the DSM and sends an arrayed output to the encoder.

8. The low-noise millimeter-wave fractional-N frequency synthesizer according to claim 7 , wherein the encoder selects a delay data D clut in the first lookup table which is closest to the phase residue φ dsm and outputs the control word corresponding to the delay data D clut as a CDTC control signal.

9. The low-noise millimeter-wave fractional-N frequency synthesizer according to claim 8 , wherein the encoder comprises a priority encoder or an adder.

10. The low-noise millimeter-wave fractional-N frequency synthesizer according to claim 8 , wherein the phase residue φ dsm minus the delay data D clut is output as a phase residue output D cdtc of the first DTC compensation module.

11. The low-noise millimeter-wave fractional-N frequency synthesizer according to claim 5 , wherein the second non-linearity calibration module includes: a second DTC compensation module and a second DTC calibration module.

12. The low-noise millimeter-wave fractional-N frequency synthesizer according to claim 11 , wherein the second DTC compensation module includes: a second lookup table, a second threshold calculation module, a second arrayed comparator, and a second encoder.

13. The low-noise millimeter-wave fractional-N frequency synthesizer according to claim 12 , wherein the second lookup table stores delay data for each control word of the corresponding FDTC, and the threshold calculation module calculates an average value of each adjacent delay data in the second lookup table and outputs the calculation result as thresholds.

14. The low-noise millimeter-wave fractional-N frequency synthesizer according to claim 13 , wherein a first phase residual output D cdtc of the first DTC compensation module is added to a current residual R dsm to obtain a pre-compared value D c , D c is compared with each threshold, and a comparison result is input to the second encoder.

15. The noise millimeter-wave fractional-N frequency synthesizer according to claim 14 , wherein the second encoder selects the delay data D fdtc closest to the compared value D c in the second lookup table and outputs a control signal of the FDTC corresponding to a control word of delayed data D fdtc .

16. The noise millimeter-wave fractional-N frequency synthesizer according to claim 15 , wherein a compared value De minus delayed data D flut comprises a phase residual R dsm of a next period, and the first phase residual output D cdtc minus the delayed data D flut is a second phase residual output D fdtc of the second DTC non-linearity compensation module.

17. The low noise millimeter-wave fractional-N frequency synthesizer according to claim 16 , wherein the first DTC calibration module compares a sign bit of the second phase residue output D fdtc with the output of the BBPD.

18. The low noise millimeter-wave fractional-N frequency synthesizer according to claim 17 , wherein when the sign bit of the second phase residue output D fdtc and the output of the BBPD are different, the first lookup table is updated such that when the output of the BBPD is 1, the delay data D clut in the first lookup table is increased according to a first preset step size, and when the output of the BBPD is 0, the delay data D clut in the first lookup table is decreased according to a second preset step size.

19. The low noise millimeter-wave fractional-N frequency synthesizer according to claim 17 , wherein the second DTC calibration module compares the sign bit of the second phase residue output D fdtc with the output of the BBPD.

20. The low noise millimeter-wave fractional-N frequency synthesizer according to claim 19 , wherein when the sign bit of the second phase residue output D fdtc and the output of the BBPD are different, the second lookup table is updated such that when the output of the BBPD is 1, the delay data D flut in the second lookup table is increased according to a third preset step size, and when the

Assignees

• Univ Electronic Science And Tech Of China
• Univ Electronic Sci & Tech China

Inventors

• Wang Zheng
• Geng Xinlin
• Ye Zonglin
• Xiao Yao
• Xie Qian

Classifications

• H03L2207/50

  All digital phase-locked loop · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/089

  the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence) · CPC title

• H03L7/1976

  using a phase accumulator for controlling the counter or frequency divider · CPC title

• Y02D30/70

  in wireless communication networks · CPC title