Delta-sigma modulator with modified quantization error shaping

Patent metadata

Field	Value
Publication number	US-12149252-B2
Application number	US-202218064823-A
Country	US
Kind code	B2
Filing date	Dec 12, 2022
Priority date	Dec 12, 2022
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

A digital phase-locked loop (DPLL) may include a delta-sigma modulator (DSM). The DSM may include a delay component configured to perform noise shaping of a quantization error introduced by the DSM. The DSM may include a noise transfer function (NTF) component configured to perform filtering of the quantization error introduced by the DSM. The DSM may include an adjustment transfer function (ATF) component configured to cause the filtering of the quantization error to be applied on top of the noise shaping such that an impact of the NTF component on the noise shaping is reduced.

First claim

What is claimed is:

1. A digital phase-locked loop (DPLL), comprising:
a delta-sigma modulator (DSM), including:
a delay component configured to perform noise shaping of a quantization error introduced by the DSM;
a noise transfer function (NTF) component configured to perform filtering of the quantization error introduced by the DSM; and
an adjustment transfer function (ATF) component configured to cause the filtering of the quantization error to be applied on top of the noise shaping such that an impact of the NTF component on the noise shaping is reduced.

2. The DPLL of claim 1 , wherein the NTF component is configured to perform notch filtering, low pass filtering, or high pass filtering.

3. The DPLL of claim 1 , wherein the DSM has a modified multi-stage noise shaping (MASH) architecture or a modified nest loop architecture.

4. The DPLL of claim 1 , wherein the noise shaping is first order noise shaping.

5. The DPLL of claim 1 , wherein the noise shaping is second order noise shaping, the delay component is a first delay component, the NTF component is a first NTF component, and the ATF component is a first ATF component, and the DSM further includes:
a second delay component associated with providing the second order noise shaping;
a second NTF component associated with performing the filtering of the quantization error; and
a second ATF component associated with reducing an impact of the second NTF component on the second order noise shaping.

6. The DPLL of claim 1 , wherein the noise shaping is third order noise shaping, the delay component is a first delay component, the NTF component is a first NTF component, and the ATF component is a first ATF component, and the DSM further includes:
a second delay component and a third delay component associated with providing the third order noise shaping;
a second NTF component and a third NTF component associated with performing the filtering of the quantization error; and
a second ATF component and a third ATF component associated with reducing an impact of the second NTF component and the third NTF component, respectively, on the third order noise shaping.

7. The DPLL of claim 1 , wherein a clock frequency of the DSM is equal to or higher than a clock frequency of a digital loop filter (DLF) of the DPLL.

8. A delta-sigma modulator (DSM), comprising:
a delay component configured to perform noise shaping of a quantization error in an output signal of the DSM;
a noise transfer function (NTF) component configured to performing filtering of the quantization error; and
an adjustment transfer function (ATF) component configured to cause the filtering of the quantization error to be applied without impairing the noise shaping.

9. The DSM of claim 8 , wherein the NTF component is configured to perform notch filtering, low pass filtering, or high pass filtering.

10. The DSM of claim 8 , wherein the DSM has a modified multi-stage noise shaping (MASH) architecture or a modified nest loop architecture.

11. The DSM of claim 8 , wherein the noise shaping is first order noise shaping.

12. The DSM of claim 8 , wherein the noise shaping is second order noise shaping, the delay component is a first delay component, the NTF component is a first NTF component, and the ATF component is a first ATF component, and the DSM further includes:
a second delay component associated with providing the second order noise shaping;
a second NTF component associated with performing the filtering of the quantization error; and
a second ATF component associated with preventing the second NTF component from impacting the second order noise shaping.

13. The DSM of claim 8 , wherein the noise shaping is third order noise shaping, the delay component is a first delay component, the NTF component is a first NTF component, and the ATF component is a first ATF component, and the DSM further includes:
a second delay component and a third delay component associated with providing the third order noise shaping;
a second NTF component and a third NTF component associated with performing the filtering of the quantization error; and
a second ATF component and a third ATF component associated with preventing the second NTF component and the third NTF component from impacting the third order noise shaping.

14. The DSM of claim 8 , wherein the DSM is included in a digital phase-locked loop (DPLL).

15. The DSM of claim 14 , wherein a clock frequency of the DSM is equal to or higher than a clock frequency of a digital loop filter (DLF) of the DPLL.

16. A method, comprising:
performing, by a delay component of a delta-sigma modulator (DSM), noise shaping of a quantization error introduced by the DSM;
performing, by a noise transfer function (NTF) component of the DSM, filtering of the quantization error introduced by the DSM; and
causing, by an adjustment transfer function (ATF) component of the DSM, the filtering of the quantization error by the NTF component to be applied in addition to the noise shaping performed by the delay component and without impairing the noise shaping.

17. The method of claim 16 , wherein the filtering is notch filtering, low pass filtering, or high pass filtering.

18. The method of claim 16 , wherein the DSM has a modified multi-stage noise shaping (MASH) architecture or a modified nest loop architecture.

19. The method of claim 16 , wherein the noise shaping is first order noise shaping.

20. The method of claim 16 , wherein the noise shaping is higher order noise shaping, and the method further comprises:
performing, by one or more additional delay components, the higher order noise shaping in conjunction with the delay component;
performing, by one or more additional NTF components, the filtering of the quantization error in conjunction with the NTF component; and
reducing, by one or more additional ATF components, an impact of the one or more additional NTF components on the higher order noise shaping in conjunction with the ATF component.

Assignees

• Infineon Technologies Ag

Inventors

• Grimaldi Luigi
• Cherniak Dmytro
• Padovan Fabio
• Boi Giovanni

Classifications

• H03L7/107

  using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth · CPC title

• H03L7/235

  Nested phase locked loops · CPC title

• H03L7/0818 Primary

  the controlled phase shifter comprising coarse and fine delay or phase-shifting means · CPC title