Analog FIR filter

Patent metadata

Field	Value
Publication number	US-12149221-B2
Application number	US-202117370565-A
Country	US
Kind code	B2
Filing date	Jul 8, 2021
Priority date	Jul 14, 2020
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

A FIR filter ( 15 ), comprising an input terminal for receiving an input signal, a first filtering circuit comprising: a first transconductance device ( 30 a ) configured to generate a first current signal (i 1 ) proportional to the input signal; a first analog switch ( 41 a ) commuted in n by a first digital gate signal (ϕ 1 ) and configured to block the current signal when the first digital gate signal has a first value and to transmit the current signal to a first integrating capacitor ( 45 a ) when the first digital gate signal has a second value; characterized in that the first digital gate signal (ϕ 1 ) comprises a periodic series of pulses, wherein the pulses have widths proportional to the filter coefficients.

First claim

The invention claimed is:

1. A FIR filter, comprising an input terminal for receiving an input signal, a first filtering circuit comprising: a first integrating capacitor, a first transconductance circuit configured to generate a first current signal proportional to the input signal; a first analog switch commuted by a first digital gate signal and configured to block the first current signal when the first digital gate signal has a first value and to transmit the first current signal to the first integrating capacitor when the first digital gate signal has a second value; wherein the first digital gate signal comprises a periodic series of pulses, wherein the pulses have widths proportional to a set of coefficients of the FIR filter.

2. The FIR filter of claim 1 , having a gate generator comprising a memory storing the set of coefficients of the FIR filter and a digital-to-time converter circuit, wherein the set of coefficients of the FIR filter are read from the memory and provided to the digital-to-time converter circuit sequentially and synchronously with a clock signal, and the digital-to-time converter circuit generates, for each received filter coefficient, a pulse having a width proportional thereto.

3. The FIR filter of claim 1 , wherein the first integrating capacitor is periodically reset.

4. The FIR filter of claim 1 , wherein the charge stored in the first integrating capacitor is periodically transferred to an output circuit.

5. The FIR filter of claim 1 , comprising a second filtering circuit comprising: a second transconductance device configured to generate a second current signal proportional to an inverted-phase replica of the input signal; a second analog switch controlled by a second digital gate signal and configured to block the second current signal when the second digital gate signal has the first value and to transmit the second current signal to the first integrating capacitor when the second digital gate signal has the second value; wherein the second digital gate signal consists in a series of pulses of constant width.

6. The FIR filter of claim 5 , wherein the second digital gate signal is generated by a second digital-to-time converter circuit whose input is static.

7. The FIR filter of claim 5 , having a second integrating capacitor, a third analog switch and a fourth analog switch controlled by digital signals and configured to transfer the first current signal and the second current signal to the first and second integrating capacitor in an interleaved fashion.

8. The FIR filter of claim 5 , having a plurality of integrating capacitors and a plurality of analog switches controlled by digital signals and configured to select cyclically an integrating capacitor from the plurality of integrating capacitors, block the first current signal when the first digital gate signal has the first value and to transmit the first current signal to the selected integrating capacitor when the first digital gate signal has the second value, block the second current signal when the second digital gate signal has the first value and to transmit the second current signal to the selected integrating capacitor when the second digital gate signal has the second value.

9. The FIR filter of claim 8 , having two integrating capacitors charged alternately.

10. The FIR filter of claim 8 , wherein the charges stored in the two integrating capacitors are cyclically transferred to an output circuit and determine a sampled output signal.

11. The FIR filter of claim 10 , having a gate generator comprising a memory storing the set of coefficients of the FIR filter and a digital-to-time converter circuit, wherein the set of coefficients of the FIR filter are read from the memory and provided to the digital-to-time converter circuit sequentially and synchronously with a clock signal, and the digital-to-time converter circuit generates, for each received filter coefficient, a pulse having a width proportional thereto, wherein a sampled output signal is decimated relative to the clock signal.

Assignees

• Semtech Corp

Inventors

• Heragu Aravind
• Vandel Eric

Classifications

• H03H2017/0081

  of FIR filters · CPC title

• H03H19/004

  Switched capacitor networks · CPC title

• H03H2015/007

  Programmable filters · CPC title

• G04F10/005

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03H17/02 Primary

  Frequency selective networks {(digital computers for complex mathematical operations G06F17/10)} · CPC title