Layout pattern of static random access memory

Patent metadata

Field	Value
Publication number	US-12148809-B2
Application number	US-202217583225-A
Country	US
Kind code	B2
Filing date	Jan 25, 2022
Priority date	Dec 23, 2021
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

The present invention provides a layout pattern of static random access memory, comprising a PU 1 (first pull-up transistor), a PU 2 (second pull-up transistor), a PD 1 A (first pull-down transistor), a PD 1 B (second pull-down transistor), a PD 2 A (third pull-down transistor), a PD 2 B (fourth pull-down transistor), a PG 1 A (first access transistor), a PG 1 B (second access transistor), a PG 2 A (third access transistor) and a PG 2 B (fourth access transistor) located on the substrate. The PD 1 A and the PD 1 B are connected in parallel with each other, the PD 2 A and the PD 2 B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

First claim

What is claimed is:

1. A layout pattern of a static random access memory (SRAM), comprising:
a plurality of fin structures located on a substrate;
a plurality of gate structures located on the substrate, wherein the plurality of gate structures span the plurality of fin structures, to form a PU 1 (first pull-up transistor), a PU 2 (second pull-up transistor), a PD 1 A (first pull-down transistor), a PD 1 B (second pull-down transistor), a PD 2 A (third pull-down transistor), a PD 2 B (fourth pull-down transistor), a PG 1 A (first access transistor), a PG 1 B (second access transistor), a PG 2 A (third access transistor) and a PG 2 B (fourth access transistor) on the substrate, wherein the PD 1 A and the PD 1 B are connected in parallel, and the PD 2 A and the PD 2 B are connected in parallel;
wherein the plurality of gate structures include a first J-shaped gate structure, the first J-shaped gate structure spans a part of the fin structures and forms the PU 1 , the PD 1 A and the PD 1 B, the first J-shaped gate structure comprises a long side structure, a short side structure and a connection structure, and the first J-shaped gate structure is an integrally formed structure; and
a third gate structure disposed beside the long side structure of the first J-shaped gate structure, and the third gate structure spans a part of the fin structures and constitutes the PG 1 B, wherein the connection structure of the first J-shaped gate structure is disposed between the third gate structure and the short side structure of the first J-shaped gate structure.

2. The layout pattern of SRAM according to claim 1 , wherein the long side structure and the short side structure are arranged along a first direction, and the connection structure and each fin structure are arranged along a second direction.

3. The layout pattern of SRAM according to claim 1 , wherein the short side structure of the first J-shaped gate structure spans a part of the fin structures and constitutes the PD 1 B.

4. The layout pattern of SRAM according to claim 1 , wherein the long side structure of the first J-shaped gate structure spans a part of the fin structures and constitutes the PU 1 and the PD 1 A.

5. The layout pattern of SRAM according to claim 2 , further comprising a second gate structure arranged along the first direction, and the second gate structure spans a part of the fin structures and constitutes the PG 1 A.

6. The layout pattern of SRAM according to claim 5 , wherein the second gate structure and the short side structure are aligned with each other in the first direction.

7. The layout pattern of SRAM according to claim 6 , wherein the third gate structure and the long side structure are aligned with each other in the first direction.

8. The layout pattern of SRAM according to claim 7 , further comprising a first local interconnection layer and a second local interconnection layer, wherein the first local interconnection layer is located between the second gate structure and the third gate structure.

9. The layout pattern of SRAM according to claim 8 , wherein the second local interconnection layer is located between the long side structure and the short side structure.

10. The layout pattern of SRAM according to claim 9 , wherein the connection structure is located between the first local interconnection layer and the second local interconnection layer.

11. The layout pattern of SRAM according to claim 8 , further comprising a metal wire electrically connecting the first local interconnection layer and the second local interconnection layer, wherein the metal wire and the connection structure are located in different layers.

Assignees

• United Microelectronics Corp

Inventors

• Huang Chun-Hsien
• Kuo Yu-Tse
• Wang Shu-Ru
• Chen Chien-Hung
• Huang Li-Ping
• Tseng Chun-Yen

Classifications

• H10D30/6211

  having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D64/518 Primary

  characterised by their lengths or sectional shapes · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H10B10/12

  comprising a MOSFET load element · CPC title