Stacks of electrically resistive materials and related systems and apparatuses

US12148789B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12148789-B2
Application numberUS-202117214322-A
CountryUS
Kind codeB2
Filing dateMar 26, 2021
Priority dateMar 26, 2021
Publication dateNov 19, 2024
Grant dateNov 19, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Stacks of electrically resistive materials and related apparatuses, electrical systems, and methods are disclosed. An apparatus includes one or more resistor devices including a substrate, first and second electrically resistive materials, and an electrically insulating material between the first and second electrically resistive materials. The substrate includes a semiconductor material. A stepped trench is defined in the substrate by sidewalls and horizontal surfaces of the semiconductor material. The first electrically resistive material and the second electrically resistive material are within the stepped trench. A method of manufacturing a resistor device includes forming a stepped trench in the substrate, forming an etch stop material within the stepped trench, disposing an electrically resistive material within the stepped trench, disposing an electrically insulating material on the electrically resistive material, and repeating the disposing the electrically resistive material and the disposing the electrically insulating material operations a predetermined number of times.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus, comprising: one or more resistor devices comprising: a substrate including a semiconductor material, a stepped trench defined in the substrate by sidewalls and horizontal surfaces of the semiconductor material; a first electrically resistive material within the stepped trench; a second electrically resistive material within the stepped trench; an electrically insulating material between the first electrically resistive material and the second electrically resistive material; and at least one electrical contact electrically connected to at least one end of the first electrically resistive material or the second electrically resistive material. 2. The apparatus of claim 1 , wherein at least one of the first electrically resistive material and the second electrically resistive material includes a polycrystalline semiconductor material. 3. The apparatus of claim 1 , wherein at least one of the first electrically resistive material and the second electrically resistive material includes polycrystalline silicon. 4. The apparatus of claim 1 , wherein the one or more resistor devices further comprise an etch stop material within the stepped trench between the substrate and the first electrically resistive material and the second electrically resistive material. 5. The apparatus of claim 1 , wherein the first electrically resistive material is electrically connected to the second electrically resistive material at one end of the stepped trench. 6. The apparatus of claim 1 , wherein the one or more resistor devices further comprise: a third electrically resistive material within the stepped trench; and another electrically insulating material between the second electrically resistive material and the third electrically resistive material. 7. The apparatus of claim 1 , wherein the substrate is terraced at one or more ends, the one or more terraced ends configured to accommodate the electrical connection of the first electrically resistive material and the second electrically resistive material through the at least one electrical contact. 8. The apparatus of claim 1 , wherein the substrate is terraced at both ends. 9. The apparatus of claim 1 , wherein the first electrically resistive material and the second electrically resistive material are arranged in a vertically oriented stack of electrically resistive materials within the stepped trench. 10. The apparatus of claim 1 , wherein the first electrically resistive material and the second electrically resistive material are arranged in a horizontally oriented stack of electrically resistive materials within the stepped trench. 11. The apparatus of claim 1 , wherein the first electrically resistive material has a different cross-sectional area from a cross-sectional area of the second electrically resistive material. 12. The apparatus of claim 1 , wherein the first electrically resistive material has a cross-sectional area that is substantially the same as a cross-sectional area of the second electrically resistive material. 13. The apparatus of claim 1 , wherein a first electrical resistance of the first electrically resistive material is substantially the same as a second electrical resistance of the second electrically resistive material. 14. The apparatus of claim 1 , wherein a first electrical resistance of the first electrically resistive material is different from a second electrical resistance of the second electrically resistive material. 15. The apparatus of claim 1 , wherein a first dopant concentration of the first electrically resistive material is substantially the same as a second dopant concentration of the second electrically resistive material. 16. The apparatus of claim 1 , wherein a first dopant concentration of the first electrically resistive material is different from a second dopant concentration of the second electrically resistive material. 17. The apparatus of claim 1 , wherein the at least one electrical contact comprises a first conductive via electrically connecting the first electrically resistive material to the second electrically resistive material at a first end of the stepped trench. 18. The apparatus of claim 17 , wherein the one or more resistor devices further comprise: a third electrically resistive material within the stepped trench; another electrically insulating material between the second electrically resistive material and the third electrically resistive material; and a second conductive via electrically connecting the second electrically resistive material to the third electrically resistive material at a second end of the stepped trench. 19. An apparatus, comprising: one or more resistor devices comprising: a substrate including a semiconductor material, a stepped trench defined in the substrate by sidewalls and horizontal surfaces of the semiconductor material; a first electrically resistive material within the stepped trench and vertically adjacent to the semiconductor material; a second electrically resistive material within the stepped trench and vertically adjacent to the first electrically resistive material, the first electrically resistive material between the semiconductor material and the second electrically resistive material; an electrically insulating material between the first electrically resistive material and the second electrically resistive; and at least one electrical contact electrically connected to at least one end of the first electrically resistive material or the second electrically resistive material. 20. The apparatus of claim 19 , wherein the one or more resistor devices further comprise a third electrically resistive material within the stepped trench, the second electrically resistive material between the first electrically resistive material and the third electrically resistive material. 21. The apparatus of claim 20 , wherein the at least one electrical contact comprises: a first electrical contact electrically connected to a first end of the first electrically resistive material; a second electrical contact electrically connected to a first end of the second electrically resistive material; a third electrical contact electrically connected to a first end of the third electrically resistive material; and a fourth electrical contact electrically connected to second ends of the first electrically resistive material, the second electrically resistive material, and the third electrically resistive material. 22. The apparatus of claim 21 , further comprising switch circuitry electrically connected to the first electrical contact, the second electrical contact, the third electrical contact, and the fourth electrical contact, the switch circuitry configured to implement a variable resistor including one or more of the first electrically resistive material, the second electrically resistive material, and the third electrically resistive material responsive to one or more control signals. 23. The apparatus of claim 22 , further comprising a controller configured to provide the one or more control signals to the switch circuitry. 24. A method of operating an electrical system, the method comprising: providing a control signal to switch circuitry, the control signal indicating a desired resistance value of a variable resistor including a stack of electrically resistive materials disposed in a stepped trench of a substrate, and at least one electrical contact electrically

Assignees

Inventors

Classifications

  • for Group V materials or Group III-V materials · CPC title

  • of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

  • of insulating materials · CPC title

  • characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

  • H10D1/47Primary

    Resistors having no potential barriers · CPC title

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What does patent US12148789B2 cover?
Stacks of electrically resistive materials and related apparatuses, electrical systems, and methods are disclosed. An apparatus includes one or more resistor devices including a substrate, first and second electrically resistive materials, and an electrically insulating material between the first and second electrically resistive materials. The substrate includes a semiconductor material. A ste…
Who is the assignee on this patent?
Micron Technology Inc
What technology area does this patent fall under?
Primary CPC classification H10D1/47. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 19 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).