Homogeneous chiplets configurable as a two-dimensional system or a three-dimensional system

Patent metadata

Field	Value
Publication number	US-12148707-B2
Application number	US-202217728761-A
Country	US
Kind code	B2
Filing date	Apr 25, 2022
Priority date	Apr 25, 2022
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

Homogeneous chiplets configurable both as a two-dimensional system or a three-dimensional system are described. An example chiplet system has a first homogeneous chiplet (HC) including a first integrated circuit (IC) die having a first logic block and a first memory that are interconnected via a first path for transfer of data signals between the first logic block and the first memory block. A second HC including a second IC die having a second logic block and a second memory block, interconnected via a second path for transfer of data signals between the second logic block and the second memory block, is stacked vertically on top of the first HC to provide a third path for transfer of data signals between the first logic block and the second memory block and a fourth path for transfer of data signals between the second logic block and the first memory block.

First claim

What is claimed:

1. A homogeneous chiplet system comprising:
a first homogeneous chiplet including a first integrated circuit die having a first logic block and a first memory block interconnected using a first on-die interconnect structure to provide a first path for transfer of data signals between the first logic block and the first memory block; and
a second homogeneous chiplet including a second integrated circuit die having a second logic block and a second memory block interconnected using a second on-die interconnect structure to provide a second path for transfer of data signals between the second logic block and the second memory block, wherein the second homogeneous chiplet is stacked vertically on top of the first homogeneous chiplet, and wherein the first logic block and the second memory block are arranged in a manner such that a first set of vertical die-to-die interconnection structures coupling the first logic block and the second memory block are configured to provide a third path for transfer of data signals between the first logic block and the second memory block, and wherein the second logic block and the first memory block are arranged in a manner such that a second set of vertical die-to-die interconnection structures coupling the second logic block and the first memory block are configured to provide a fourth path for transfer of data signals between the second logic block and the first memory block.

2. The homogeneous chiplet system of claim 1 , wherein the first path has a first expected latency associated with the transfer of data signals between the first logic block and the first memory block, wherein the third path has a second expected latency associated with the transfer of data signals between the first logic block and the second memory block, and wherein the first expected latency is greater than the second expected latency.

3. The homogeneous chiplet system of claim 1 , wherein the second path has a first expected latency associated with the transfer of data signals between the second logic block and the second memory block, wherein the fourth path has a second expected latency associated with the transfer of data signals between the second logic block and the first memory block, and wherein the first expected latency is greater than the second expected latency.

4. The homogeneous chiplet system of claim 1 , wherein the first memory block comprises a first 2-port static random access memory (SRAM), and wherein the second memory block comprises a second 2-port SRAM.

5. The homogeneous chiplet system of claim 1 , wherein the first homogeneous chiplet further comprises a first memory interface for coupling the first homogeneous chiplet to a first memory external to the first homogeneous chiplet.

6. The homogeneous chiplet system of claim 1 , wherein the second homogeneous chiplet further comprises a second memory interface for coupling the second homogeneous chiplet to a second memory external to the second homogeneous chiplet.

7. The homogeneous chiplet system of claim 1 , wherein the first integrated circuit die is configured such that the first integrated circuit die can be both vertically coupled to another integrated circuit die and horizontally coupled to a yet another integrated circuit die.

8. The homogeneous chiplet system of claim 1 , wherein the second integrated circuit die is configured such that the second integrated circuit die can be both vertically coupled to another integrated circuit die and horizontally coupled to a yet another integrated circuit die.

9. A homogeneous chiplet system comprising:
a first homogeneous chiplet including a first integrated circuit die having a first logic block and a first memory block interconnected using a first on-die interconnect structure to provide a first path for transfer of data signals between the first logic block and the first memory block; and
a second homogeneous chiplet including a second integrated circuit die having a second logic block and a second memory block interconnected using a second on-die interconnect structure to provide a second path for transfer of data signals between the second logic block and the second memory block, wherein the second homogeneous chiplet is stacked vertically on top of the first homogeneous chiplet, and wherein the first logic block and the second memory block are arranged in a manner such that a first set of vertical die-to-die interconnection structures coupling the first logic block and the second memory block are configured to provide a third path for transfer of data signals between the first logic block and the second memory block, and wherein the second logic block and the first memory block are arranged in a manner such that a second set of vertical die-to-die interconnection structures coupling the second logic block and the first memory block are configured to provide a fourth path for transfer of data signals between the second logic block and the first memory block, wherein the first path has a first expected latency associated with the transfer of data signals between the first logic block and the first memory block, wherein the third path has a second expected latency associated with the transfer of data signals between the first logic block and the second memory block, wherein the first expected latency is greater than the second expected latency, wherein the second path has a first expected latency associated with the transfer of data signals between the second logic block and the second memory block, wherein the fourth path has a second expected latency associated with the transfer of data signals between the second logic block and the first memory block, and wherein the first expected latency is greater than the second expected latency.

10. The homogeneous chiplet system of claim 9 , wherein the first memory block comprises a first 2-port static random access memory (SRAM), and wherein the second memory block comprises a second 2-port SRAM.

11. The homogeneous chiplet system of claim 9 , wherein the first homogeneous chiplet further comprises a first memory interface for coupling the first homogeneous chiplet to a first memory external to the first homogeneous chiplet.

12. The homogeneous chiplet system of claim 9 , wherein the second homogeneous chiplet further comprises a second memory interface for coupling the second homogeneous chiplet to a second memory external to the second homogeneous chiplet.

13. The homogeneous chiplet system of claim 9 , wherein the first integrated circuit die is configured such that the first integrated circuit die can be both vertically coupled to another integrated circuit die and horizontally coupled to a yet another integrated circuit die.

14. The homogeneous chiplet system of claim 9 , wherein the second integrated circuit die is configured such that the second integrated circuit die can be both vertically coupled to another integrated circuit die and horizontally coupled to a yet another integrated circuit die.

15. A homogeneous chiplet system comprising:
a first homogeneous chiplet including a first integrated circuit die having a first logic block and a first memory block interconnected using a first on-die interconnect structure to provide a first path for transfer of data signals between the first logic block and the first memory block; and
a second homogeneous chiplet including a second integrated circuit die having a second logic block and a second memory block interconnected using a second on-die interconnect structure to provide a second path for transfer of data signals between the second logic block and the second memory block, wherein the se

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Zhou Haohua
• Xu Xiaoling

Classifications

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title