Readout from memory cells subjected to perturbations in threshold voltage distributions

Patent metadata

Field	Value
Publication number	US-12148496-B2
Application number	US-202217852647-A
Country	US
Kind code	B2
Filing date	Jun 29, 2022
Priority date	Jun 29, 2022
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

A memory controller includes an interface and a processor. The interface is configured to communicate with a plurality of memory cells. The processor is configured to, using multiple Read Thresholds (RTs) positioned between adjacent Programming Voltages (PVs), produce (i) a base parametric model of Threshold Voltage Distributions (TVDs) associated with the PVs, and (ii) auxiliary information that depends on the RTs and on the base parametric model, to read a group of the memory cells using the RTs to produce multiple readouts, the threshold voltages of the memory cells in the group are distributed in accordance with actual TVDs, to derive from the base parametric model an actual parametric model, based on the multiple readouts and on the auxiliary information, and determine a readout parameter based on the actual parametric model, and to perform a read-related operation using the readout parameter.

First claim

The invention claimed is:

1. A memory controller, comprising:
an interface, configured to communicate with a plurality of memory cells; and
a processor, configured to:
read a group of the memory cells to produce multiple readouts, using multiple Read Thresholds (RTs) positioned between adjacent Programming Voltages (PVs), in accordance with a base parametric model, wherein the multiple readouts comprise bits of code words and confidence levels assigned respectively to the bits of code words;
determine a deviation between the base parametric model and an estimated actual parametric model in response to the multiple readouts; and
correct the confidence levels of the multiple readouts in response to the determined deviation.

2. The memory controller according to claim 1 , wherein the base parametric model and the actual parametric model comprise multiple parameters.

3. The memory controller according to claim 1 , wherein the processor is configured to count for each of a plurality of voltage zones between adjacent RTs, a number of memory cells for which the multiple readouts fall in the voltage zone, to calculate normalized cell-counts based on the count, and to determine the deviation based on the normalized cell-counts and on auxiliary information.

4. The memory controller according to claim 3 , wherein the auxiliary information comprises an auxiliary vector and an auxiliary matrix, and wherein the processor is configured to determine the deviation by (i) calculating a difference vector between the normalized cell-counts and respective elements in the auxiliary vector, and (ii) multiplying between the auxiliary matrix and the difference vector.

5. The memory controller according to claim 4 , wherein the processor is configured to produce based on the auxiliary matrix, a sequence of updated auxiliary matrices over multiple iterations, and to determine the deviation using an updated auxiliary matrix.

6. The memory controller according to claim 1 , wherein the processor is configured to evaluate a criterion for updating the base parametric model, and to produce an updated base parametric model in response to meeting the criterion.

7. The memory controller according to claim 1 , wherein the processor is configured to read one or more other groups of the memory cells using the actual parametric model.

8. The memory controller according to claim 1 , wherein the processor is configured to hold separate base confidence levels for multiple respective subsets of the memory cells in the group, the subsets correspond to different threshold voltages of neighbor memory cells, to derive from the base confidence levels of the subsets corrected confidence levels, based on one or more actual parametric models, and to perform soft decoding to a given code word read from the group of the memory cells using the corrected confidence levels.

9. The memory controller according to claim 8 , wherein the processor is configured to calculate for the subsets separate respective actual parametric models, and to derive the corrected confidence levels in a given subset based on the actual parametric model associated with the given subset.

10. The memory controller according to claim 1 , wherein the processor is configured to soft decode the code words from the bits, using the corrected confidence levels.

11. The memory controller according to claim 1 , wherein the processor is configured to count a number of the group of the memory cells in each of a plurality of voltage zones, and to determine the deviation in response to the count of the number of the group of the memory cells in each of a plurality of voltage zones.

12. A method for data storage, comprising:
in a memory controller that communicates with a plurality of memory cells, reading a group of the memory cells to produce multiple readouts, using multiple Read Thresholds (RTs) positioned between adjacent Programming Voltages (PVs) in accordance with a base parametric model, wherein the multiple readouts comprise bits of code words and confidence levels assigned respectively to the bits of code words;
determining a deviation between the base parametric model and an estimated actual parametric model in to the multiple readouts; and
correcting the confidence levels of the multiple readouts in response to the determined deviation.

13. The method according to claim 12 , wherein the base parametric model and the actual parametric model comprise multiple parameters.

14. The method according to claim 12 , wherein determining the deviation comprises calculating, based on the multiple readouts, normalized cell-counts of memory cells in the group having readouts that fall in respective zones defined between adjacent RTs, and determining the deviation based on the normalized cell-counts and on auxiliary information.

15. The method according to claim 14 , wherein the auxiliary information comprises an auxiliary vector and an auxiliary matrix, and wherein determining the deviation comprises (i) calculating a difference vector between the normalized cell-counts and respective elements in the auxiliary vector, and (ii) multiplying between the auxiliary matrix and the difference vector.

16. The method according to claim 15 , and comprising producing based on the auxiliary matrix, a sequence of updated auxiliary matrices over multiple iterations, and determining the deviation using an updated auxiliary matrix.

17. The method according to claim 12 , and comprising evaluating a criterion for updating the base parametric model, and producing an updated base parametric model in response to meeting the criterion.

18. The method according to claim 12 , and comprising reading one or more other groups of the memory cells using the actual parametric model.

19. The method according to claim 12 , and comprising holding separate base confidence levels for multiple respective subsets of the memory cells in the group, the subsets correspond to different threshold voltages of neighbor memory cells, deriving from the base confidence levels of the subsets corrected confidence levels, based on one or more actual parametric models, and performing soft decoding to a given code word read from the group of the memory cells using the corrected confidence levels.

20. The method according to claim 19 , and comprising calculating for the subsets separate respective actual parametric models, and deriving the corrected confidence levels in a given subset based on the actual parametric model associated with the given subset.

Assignees

• Apple Inc

Inventors

• Tishbi Nir
• Roth Roy
• Tate Yonathan

Classifications

• G11C7/1069

  I/O lines read out arrangements · CPC title

• G11C2029/5004

  Voltage · CPC title

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title

• G11C11/5671

  using charge trapping in an insulator · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title