Display device

Patent metadata

Field	Value
Publication number	US-12148381-B2
Application number	US-202318238203-A
Country	US
Kind code	B2
Filing date	Aug 25, 2023
Priority date	Nov 30, 2022
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

A display device can include a plurality of sub pixels disposed on a substrate; a first driver disposed in each of the plurality of sub pixels, the first driver being configured to generate a first driving current for a normal mode in which an image is displayed in a luminance range equal to or lower than a predetermined luminance; a second driver disposed in each of the plurality of sub pixels, the second driver being configured to generate a second driving current for a high luminance mode in which the luminance range is higher than the predetermined luminance; and a light emitting diode. Also, the light emitting diode is configured to receive the first driving current in the normal mode, and receive a sum of the first driving current and the second driving current in the high luminance mode.

First claim

What is claimed is:

1. A display device comprising:
a plurality of sub pixels disposed on a substrate;
a first driver disposed in each of the plurality of sub pixels, the first driver being configured to generate a first driving current for a normal mode in which an image is displayed in a luminance range equal to or lower than a predetermined luminance;
a second driver disposed in each of the plurality of sub pixels, the second driver being configured to generate a second driving current for a high luminance mode in which the luminance range is higher than the predetermined luminance; and
a light emitting diode configured to:
receive the first driving current in the normal mode, and
receive a sum of the first driving current and the second driving current in the high luminance mode,
wherein the first driver includes:
a first driving transistor having a source electrode connected to a first node, a gate electrode connected to a second node, and a drain electrode connected to a third node;
a first transistor connected between the second node and the third node;
a second transistor connected between the first node and a data line;
a third transistor connected between the first node and a high potential power line;
a fourth transistor connected between the third node and a fourth node, the fourth node being an anode of the light emitting diode;
a fifth transistor connected between the second node and a first initialization line;
a sixth transistor connected between the fourth node and the first initialization line; and
a first capacitor connected between the second node and the high potential power line, and

wherein the second driver includes a second driving transistor which is connected to the first driving transistor in parallel.

2. The display device according to claim 1 , wherein during the normal mode, the first driver is turned on and the second driver is turned off, and
wherein during the high luminance mode, the first driver and the second driver are both turned on.

3. The display device according to claim 1 , wherein the second driving transistor includes a gate electrode connected to a fifth node, a source electrode connected to the first node, and a drain electrode connected to a sixth node, and
wherein the second driver further includes:
a seventh transistor connected between the fifth node and the sixth node;
an eighth transistor connected between the sixth node and the fourth node;
a ninth transistor connected between the fifth node and the second initialization line; and
a second capacitor connected between the fifth node and the high potential power line.

4. The display device according to claim 3 , further comprising:
an emission control line connected to a gate electrode of the fourth transistor and a gate electrode of the eighth transistor;
a n-th scan line connected to a gate electrode of the first transistor and a gate electrode of the seventh transistor; and
a n-3-th scan line connected to a gate electrode of the fifth transistor and a gate electrode of the ninth transistor.

5. The display device according to claim 4 , wherein the gate electrode of the third transistor, the gate electrode of the fourth transistor and the gate electrode of the eight transistor are all connected to the emission control line.

6. The display device according to claim 3 , wherein during the normal mode driving, a first initialization voltage is output from the first initialization line and a first voltage is output from the second initialization line, and
wherein the first voltage has a same voltage as a high potential power voltage of the high potential power line.

7. The display device according to claim 6 , wherein during the high luminance mode, the first initialization voltage is output from the first initialization line and a second voltage is output from the second initialization line, and
wherein the second voltage has a same voltage as the first initialization voltage.

8. The display device according to claim 3 , wherein during the normal mode, a turn-off level voltage is applied to the gate electrode of the second driving transistor.

9. The display device according to claim 3 , wherein the first and second driving transistors and the first through ninth transistors are p-type transistors.

10. The display device according to claim 1 , wherein a first ratio of a width of a channel of the first driving transistor to a length of the channel of the first driving transistor is approximately equal to a second ratio of a width of a channel of the second driving transistor to a length of the channel of the second driving transistor.

11. The display device according to claim 1 , wherein a first length of a channel of the first driving transistor is longer than a second length of a channel of the second driving transistor.

12. The display device according to claim 1 , wherein a first ratio of a width of a channel of the first driving transistor to a length of the channel of the first driving transistor is smaller than a second ratio of a width of a channel of the second driving transistor to a length of the channel of the second driving transistor.

13. The display device according to claim 1 , wherein each of a first active layer of the first driving transistor and a second active layer of the second driving transistor includes an oxide semiconductor material.

14. A method of controlling a display device, the method comprising:
displaying an image on a display panel including a plurality of subpixels, each of the plurality of subpixels including a first driver to supply a first current and a second driver to supply a second current;
in response to an ambient level of light around the display device being less than a predetermined light level, activating the first driver in each of the plurality of subpixels and supplying the first current to the plurality of subpixels via the corresponding first driver while the second driver is deactivated; and
in response to the ambient level of light around the display device being greater than a predetermined light level, activating both of the first driver and the second driver in each of the plurality of subpixels and supplying a sum of the first current and the second current to the plurality of subpixels via the corresponding first driver and the corresponding second driver,
wherein the first driver includes:
a first driving transistor having a source electrode connected to a first node, a gate electrode connected to a second node, and a drain electrode connected to a third node;
a first transistor connected between the second node and the third node;
a second transistor connected between the first node and a data line;
a third transistor connected between the first node and a high potential power line;
a fourth transistor connected between the third node and a fourth node, the fourth node being an anode of the light emitting diode;
a fifth transistor connected between the second node and a first initialization line;
a sixth transistor connected between the fourth node and the first initialization line; and
a first capacitor connected between the second node and the high potential power line, and

wherein the second driver includes a second driving transistor which is connected to the first driving transistor in parallel.

15. The method of claim 14 , wherein a first ratio of a width of a channel of the first driving transistor to a length of the channel of the first driving transistor is approximately equal to a second ratio of a width of a channel of the second driving transistor to a length of the channel of the second d

Assignees

• Lg Display Co Ltd

Inventors

• Kim Jiah
• Choi Joungmi

Classifications

• G09G2300/0852

  being a dynamic memory with more than one capacitor · CPC title

• G09G2320/0626

  for control of overall brightness · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2360/144

  the light being ambient light · CPC title