Scan circuit and display apparatus

Patent metadata

Field	Value
Publication number	US-12148358-B2
Application number	US-202117760495-A
Country	US
Kind code	B2
Filing date	Nov 1, 2021
Priority date	Nov 1, 2021
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

A scan circuit is provided. The scan circuit includes a plurality of stages. A respective stage of the scan circuit includes a second processing subcircuit, which includes a first capacitor, a sixth transistor, and a seventh transistor. The respective stage of the scan circuit further includes a sixth connecting line connecting a first electrode of the seventh transistor, a second electrode of the sixth transistor, and a second capacitor electrode of the first capacitor together. The sixth connecting line crosses over both the first capacitor electrode and the second capacitor electrode of the first capacitor.

First claim

What is claimed is:

1. A scan circuit, comprising a plurality of stages;
wherein a respective stage of the scan circuit comprises a second processing subcircuit, which comprises a first capacitor, a sixth transistor, and a seventh transistor;
a first terminal of the first capacitor is coupled to a sixth node, and a second terminal of the first capacitor is coupled to a third node;
a gate electrode of the sixth transistor is coupled to the sixth node;
a first electrode of the sixth transistor is coupled to a third input terminal;
a second electrode of the sixth transistor is coupled to the third node;
a gate electrode of the seventh transistor is coupled to the third input terminal;
a first electrode of the seventh transistor is coupled to the third node;
a second electrode of the seventh transistor is coupled to a fourth node;
the respective stage of the scan circuit further comprises a sixth connecting line connecting a first electrode of the seventh transistor, a second electrode of the sixth transistor, and a second capacitor electrode of the first capacitor together; and
the sixth connecting line crosses over both a first capacitor electrode and the second capacitor electrode of the first capacitor;
wherein the first capacitor electrode of the first capacitor and the gate electrode of the sixth transistor are parts of a unitary structure; and
the first capacitor electrode of the first capacitor has a L shape, a first part of the first capacitor electrode extending substantially along a first direction, a second part of the first capacitor electrode extending substantially along a second direction;
wherein the respective stage of the scan circuit further comprises an input subcircuit comprising a first transistor, and an input signal line configured to provide an input signal to the first transistor, a portion of the input signal line extending substantially along the second direction;
a gate electrode of the first transistor is coupled to a second input terminal;
a first electrode of the first transistor is coupled to a first input terminal;
a second electrode of the first transistor is coupled to a fifth node; and
a ratio of a width along the first direction of the first part to a shortest distance between the first part and the portion extending substantially along the second direction is no more than 2.0:1.

2. The scan circuit of claim 1 , wherein the second capacitor electrode of the first capacitor has a L shape, a third part of the second capacitor electrode extending substantially along a first direction, a fourth part of the second capacitor electrode extending substantially along the second direction; and
a ratio of a width along the first direction of the third part to a shortest distance between the third part and the portion extending substantially along the second direction is no more than 2.0:1.

3. The scan circuit of claim 1 , wherein an overlapping area between a first capacitor electrode and the second capacitor electrode of the first capacitor is no more than 400 μm 2 .

4. The scan circuit of claim 1 , wherein a portion of a semiconductor material layer comprising an active layer of the sixth transistor has a dumbbell shape;
the portion of the semiconductor material layer is connected to a first electrode and a second electrode of the sixth transistor respective at positions corresponding to two heads of the dumbbell shape;
a rod connecting the two heads comprises the active layer of the sixth transistor; and
widths along a second direction of the two heads are greater than a width along the second direction of the rod.

5. The scan circuit of claim 1 , wherein a ratio of channel width to channel length of an active layer of the sixth transistor is in a range of 0.8:1 to 1:0.8.

6. The scan circuit of claim 1 , wherein the respective stage of the scan circuit further comprises an output subcircuit, which comprises a ninth transistor;
a first electrode of the ninth transistor is configured to be provided with a first power supply signal;
a gate electrode of the ninth transistor is coupled to the fourth node;
a second electrode of the ninth transistor is coupled to an output terminal;
an active layer of the ninth transistor comprises m numbers of channels parts spaced apart from each other, m is an integer greater than 2;
a respective channel part of the active layer of the ninth transistor has a channel width and a channel length; and
a ratio of (m*the channel width of the respective channel part) to the channel length of the respective channel part is greater than 22:1.

7. The scan circuit of claim 1 , wherein the respective stage of the scan circuit further comprises an output subcircuit, which comprises a tenth transistor;
a first electrode of the tenth transistor is configured to be provided with a second power supply signal;
a gate electrode of the tenth transistor is coupled to a first node;
a second electrode of the tenth transistor is coupled to an output terminal;
an active layer of the tenth transistor comprises n numbers of channels parts spaced apart from each other, n is an integer greater than 2;
a respective channel part of the active layer of the tenth transistor has a channel width and a channel length; and
a ratio of (n*the channel width of the respective channel part) to the channel length of the respective channel part is greater than 13:1.

8. A scan circuit, comprising a plurality of stages;
wherein a respective stage of the scan circuit comprises a second processing subcircuit, which comprises a first capacitor, a sixth transistor, and a seventh transistor;
a first terminal of the first capacitor is coupled to a sixth node, and a second terminal of the first capacitor is coupled to a third node;
a gate electrode of the sixth transistor is coupled to the sixth node;
a first electrode of the sixth transistor is coupled to a third input terminal;
a second electrode of the sixth transistor is coupled to the third node;
a gate electrode of the seventh transistor is coupled to the third input terminal;
a first electrode of the seventh transistor is coupled to the third node;
a second electrode of the seventh transistor is coupled to a fourth node;
the respective stage of the scan circuit further comprises a sixth connecting line connecting a first electrode of the seventh transistor, a second electrode of the sixth transistor, and a second capacitor electrode of the first capacitor together; and
the sixth connecting line crosses over both the first capacitor electrode and the second capacitor electrode of the first capacitor;
wherein the respective stage of the scan circuit further comprises an input subcircuit comprising a first transistor, and an input signal line configured to provide an input signal to the first transistor;
a gate electrode of the first transistor is coupled to a second input terminal;
a first electrode of the first transistor is coupled to a first input terminal;
a second electrode of the first transistor is coupled to a fifth node; and
the input signal line comprises a first line portion and a second line portion in two different layers, respectively; and
the second line portion comprises at least a portion of the input signal line extending along a part of a periphery of a first capacitor electrode of the first capacitor in a preceding stage of the scan circuit.

9. The scan circuit of claim 1 , wherein the respective stage of the scan circuit further comprises:
an output subcircuit, which comprises a ninth transistor and a tenth transistor;
a first electrode of the ninth transistor is configured to be provided with a first power supply signal;
a gate electrode of the ninth transistor is coupled to the four

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Huang Yao
• Li Meng
• Cheng Tianyi
• Kim Doyoung
• Ma Long

Classifications

• G09G2320/0223

  Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title