Method for power reduction in memory modules

Patent metadata

Field	Value
Publication number	US-12147684-B2
Application number	US-202217962387-A
Country	US
Kind code	B2
Filing date	Oct 7, 2022
Priority date	Oct 7, 2022
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

A clock buffer device for a memory module includes a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL. An output of the first PLL is selectably coupled to clock output buffers, and an output of the second PLL is selectably coupled to a subset of the clock output buffers. The clock buffer device receives a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and, in response to the indication, couples the output of the first PLL to the clock output buffers and to disables the second PLL.

First claim

What is claimed is:

1. A clock buffer device for a memory module, the clock buffer device comprising:
a first clock input coupled to an input of a first phase-locked loop (PLL), an output of first PLL being selectably coupled to a plurality of clock output buffers; and
a second clock input coupled to an input of a second PLL, an output of the second PLL being selectably coupled to a first subset of the clock output buffers;
wherein the clock buffer device is configured to receive a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and in response to the first indication, to couple the output of the first PLL to the clock output buffers and to disable the second PLL.

2. The clock buffer device of claim 1 , wherein the first indication is received from the first information handling system.

3. The clock buffer device of claim 1 , further configured to receive a second indication that a second information handling system is configured to provide a third clock signal on the first clock input and to provide a fourth clock signal on the second clock input, and in response to the second indication, to couple the first PLL to a second subset of the clock output buffers and to couple the second PLL to the first subset of the clock output buffers, wherein the first subset and the second subset are non-overlapping subsets, and wherein the first subset and the second subset include all of the clock output buffers.

4. The clock buffer device of claim 3 , wherein the second indication is received from the second information handling system.

5. The clock buffer device of claim 3 , wherein the first subset of the clock output buffers is associated with a first memory sub-channel, and the second subset of clock output buffers is associated with a second memory sub-channel.

6. The clock buffer device of claim 1 , further configured to instantiate a state machine to receive the first indication and the second indication.

7. The clock buffer device of claim 6 , wherein the state machine receives the first indication and the second indication from a two-wire interface.

8. The clock buffer device of claim 7 , wherein the two-wire interface is an inter-integrated circuit interface.

9. The clock buffer device of claim 1 , wherein the clock buffer device is included in a memory module.

10. The clock buffer device of claim 9 , wherein the memory module is a fifth generation double data rate memory module.

11. A method, comprising:
coupling a first clock input of a clock buffer device of a memory module to an input of a first phase-locked loop (PLL);
selectably coupling an output of first PLL to a plurality of clock output buffers;
coupling a second clock input of the clock buffer device to an input of a second PLL;
selectably coupling an output of second PLL to a first subset of the clock output buffers;
receiving, by the clock buffer device, a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input; and
in response to the first indication;
coupling the output of the first PLL to the clock output buffers; and
disabling the second PLL.

12. The method of claim 11 , wherein the first indication is received from the first information handling system.

13. The method of claim 11 , further comprising:
receiving a second indication that a second information handling system is configured to provide a third clock signal on the first clock input and to provide a fourth clock signal on the second clock input; and
coupling the first PLL to a second subset of the clock output buffers and to couple the second PLL to the first subset of the clock output buffers in response to the second indication, wherein the first subset and the second subset are non-overlapping subsets, and wherein the first subset and the second subset include all of the clock output buffers.

14. The method of claim 13 , wherein the second indication is received from the second information handling system.

15. The method of claim 13 , wherein the first subset of the clock output buffers is associated with a first memory sub-channel, and the second subset of clock output buffers is associated with a second memory sub-channel.

16. The method of claim 11 , further comprising receiving, by a state machine of the clock buffer device, the first indication and the second indication.

17. The method of claim 16 , further comprising receiving, by the state machine, the first indication and the second indication from a two-wire interface.

18. The method of claim 17 , wherein the two-wire interface is an Inter-Integrated Circuit (I2C) interface.

19. The method of claim 11 , wherein the clock buffer device is included in a memory module.

20. A memory module, comprising:
a plurality of memory devices; and
a clock buffer including:
a first clock input coupled to an input of a first phase-locked loop (PLL), an output of first PLL being selectably coupled to a plurality of clock output buffers, each clock output buffer being coupled to one or more of the memory devices; and
a second clock input coupled to an input of a second PLL, an output of the second PLL being selectably coupled to a first subset of the clock output buffers;

wherein the clock buffer device is configured to receive an indication that an information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and, in response to the indication, to couple the output of the first PLL to the clock output buffers and to disable the second PLL.

Assignees

• Dell Products Lp

Inventors

• Wang Isaac Q
• Zaretsky Lee B

Classifications

• G06F3/0673

  Single storage device · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title