Error processing for non-volatile memories

Patent metadata

Field	Value
Publication number	US-12147303-B2
Application number	US-202318159365-A
Country	US
Kind code	B2
Filing date	Jan 25, 2023
Priority date	Jan 26, 2022
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

A solution is proposed for error processing, wherein n byte error positions of n byte errors are predefined (where n is a positive integer), wherein this involves determining whether there is a further byte error position on the basis of the n byte error positions and on the basis of n+1 error syndrome components of a first error code.

First claim

The invention claimed is:

1. A method for error processing,
reading a plurality of bytes from a memory;
wherein n byte error positions of n byte errors are predetermined, wherein n is a positive integer,
which method involves determining whether there is a further byte error position on the basis of the n byte error positions and on the basis of n+1 error syndrome components of a first error code, and
in the event of determining a further byte error position,
(a) correcting a byte of the plurality of bytes read from the memory at the further byte error position and/or
(b) outputting the further byte error position.

2. The method according to claim 1 , wherein the further byte error position is determined by way of the n byte error positions and the n+1 error syndrome components of the first error code.

3. The method according to claim 1 , wherein the first error code comprises a byte error code, wherein the byte error code comprises a Reed-Solomon code.

4. The method according to claim 1 , which involves detecting that no further byte error is present if no further byte error position is determinable.

5. The method according to claim 1 , wherein the further byte error position is determined depending on at least one symmetrical function of the n byte error positions.

6. The method according to claim 5 , wherein, if a non-code word of the second error code is detected in the course of the reading out from the memory, a byte error position is determined for this byte of the first error code.

7. The method according to claim 1 , wherein
in the error-free case a byte of the first error code is transformed into a code word of a second error code,
a byte error position is determined if a non-code word of the second error code is detected.

8. The method according to claim 7 , wherein code words of the second error code are stored in a memory.

9. The method according to claim 1 , wherein the second error code is an n 1 -out-of-n 2 code, wherein 1≤n 1 <n 2 ≤2 holds true.

10. The method according to claim 9 , wherein the reading out from the memory is effected taking account of a temporal order.

11. The method according to claim 1 , wherein in the error-free case code words of the second error code are read out from the memory and transformed back into bytes of the first error code.

12. The method according to claim 1 , wherein the further byte error position az is determinable such that the following holds true:

α
2

=

s
3

+

s
2

·

α
1

s
1

·

α
1

+

s
2

,

wherein α 1 denotes the predefined byte error position and s 1 , s 2 , s 3 denote syndrome components.

13. The memory circuit comprising:
a memory for storing a plurality of memory bytes, and
a device for error processing, which is configured to determine whether there is a further byte error position on the basis of n byte error positions and on the basis of n+1 error syndrome components of a first error code, wherein the n byte error positions of n byte errors are predefined and wherein n is a positive integer.

14. The memory circuit according to claim 13 , wherein the device is furthermore configured to determine the further byte error position by way of the n byte error positions and the n+1 error syndrome components of the first error code.

15. A non-transitory computer-readable storage medium having instructions stored thereon that, when executed, cause one or more processors to:
store a plurality of memory bytes; and
determine whether there is a further byte error position on a basis of n byte error positions and on a basis of n+1 error syndrome components of a first error code, wherein the n byte error positions of the n byte errors are predefined and wherein n is a positive integer.

Assignees

• Infineon Technologies Ag

Inventors

• Kern Thomas
• Goessel Michael
• Klockmann Alexander
• Rabenalt Thomas

Classifications

• H04L1/0045

  Arrangements at the receiver end · CPC title

• H04L1/0041

  Arrangements at the transmitter end · CPC title

• H04L1/0065

  Serial concatenated codes · CPC title

• H04L1/0057

  Block codes (H04L1/0061, H04L1/0064 take precedence) · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title