Decoding method, decoding device, and readable storage medium

Patent metadata

Field	Value
Publication number	US-12143129-B2
Application number	US-202117600117-A
Country	US
Kind code	B2
Filing date	May 31, 2021
Priority date	Jan 19, 2021
Publication date	Nov 12, 2024
Grant date	Nov 12, 2024

Abstract

This application discloses a decoding method, a decoding device, and a readable storage medium. The decoding method can perform a simple logic operation on the corresponding specified bits in the first bitstream, and generate the corresponding fourth bitstream accordingly to obtain information before encoding. The logic design of this decoding method is simple, which can reduce the complexity of logic circuit design and improve the reliability of decoding.

First claim

What is claimed is:

1. A decoding method comprising:
obtaining a second bitstream based on a first bitstream, wherein the first bitstream comprises a first specified bit, a second specified bit, a third specified bit, and a fourth specified bit;
processing the second bitstream to obtain a third bitstream based on a result of a first logical operation of the first specified bit and the second specified bit in the first bitstream; and
processing the third bitstream to obtain a fourth bitstream based on a result of a second logical operation of the third specified bit and the fourth specified bit in the first bitstream, wherein the fourth bitstream comprises eight bits.

2. The decoding method according to claim 1 , wherein the step of obtaining the second bitstream based on the first bitstream comprises:
determining two flag bits in the first bitstream, wherein the two flag bits are not the first specified bit, the second specified bit, the third specified bit, and the fourth specified bit in the first bitstream; and
discarding the two flag bits to obtain the second bitstream.

3. The decoding method according to claim 1 , wherein the step of processing the second bitstream to obtain the third bitstream based on the result of the first logical operation of the first specified bit and the second specified bit comprises:
outputting the second bitstream as the third bitstream when the result of the first logical operation is logical false; and
obtaining an inverse of a second bit number and an inverse of a fourth bit number in the first bitstream correspondingly as a value assigned to a first bit and a value assigned to a third bit in the second bitstream and outputting the second bitstream with the assigned values as the third bitstream when the result of the first logical operation is logical true.

4. The decoding method according to claim 3 , wherein the step of processing the second bitstream to obtain the third bitstream based on the result of the first logical operation of the first specified bit and the second specified bit further comprises:
determining that the first specified bit and the second specified bit correspond to a zeroth bit and a first bit; and
exclusive-or-operating the zeroth bit with the first bit to obtain the result of the first logical operation.

5. The decoding method according to claim 1 , wherein the step of processing the third bitstream to obtain the fourth bitstream based on the result of the second logical operation of the third specified bit and the fourth specified bit comprises:
outputting the third bitstream as the fourth bitstream when the result of the second logical operation is logical false; and
obtaining an inverse of a seventh bit number and an inverse of a ninth bit number in the first bitstream correspondingly as a value assigned to a fifth bit and a value assigned to a seventh bit in the third bitstream and outputting the third bitstream with the assigned values as the fourth bitstream when the result of the second logical operation is logical true.

6. The decoding method according to claim 5 , wherein the step of processing the third bitstream to obtain the fourth bitstream based on the result of the second logical operation of the third specified bit and the fourth specified bit further comprises:
determining that the third specified bit and the fourth specified bit correspond to a fifth bit and a sixth bit; and
exclusive-or-operating the fifth bit with the sixth bit to obtain the result of the second logical operation.

7. The decoding method according to claim 1 , wherein the first bitstream comprises ten bits.

8. The decoding method according to claim 7 , wherein a number of bits included in the fourth bitstream are the same as a number of bits included in the second bitstream and/or the third bitstream.

9. A decoding device comprising a processor, wherein the processor is configured to execute instructions to implement a decoding method as claimed in claim 1 .

10. A decoding device according to claim 9 , wherein the step of obtaining the second bitstream based on a first bitstream comprises:
determining two flag bits in the first bitstream, wherein the two flag bits are not the first specified bit, the second specified bit, the third specified bit, and the fourth specified bit in the first bitstream; and
discarding the two flag bits to obtain the second bitstream.

11. The decoding device according to claim 9 , wherein the step of processing the second bitstream to obtain the third bitstream based on the result of the first logical operation of the first specified bit and the second specified bit comprises:
outputting the second bitstream as the third bitstream when the result of the first logical operation is logical false;
obtaining an inverse of a second bit number and an inverse of a fourth bit number in the first bitstream correspondingly as a value assigned to a first bit and a value assigned to a third bit in the second bitstream and outputting the second bitstream with the assigned values as the third bitstream when the result of the first logical operation is logical true.

12. The decoding device according to claim 11 , wherein the step of processing the second bitstream to obtain the third bitstream based on the result of the first logical operation of the first specified bit and the second specified bit further comprises:
determining that the first specified bit and the second specified bit corresponds to a zeroth bit and a first bit; and
exclusive-or-operating the zeroth bit with the first bit to obtain the result of the first logical operation.

13. The decoding device according to claim 9 , wherein the step of processing the third bitstream to obtain the fourth bitstream based on the result of the second logical operation of the third specified bit and the fourth specified bit comprises:
outputting the third bitstream as the fourth bitstream when the result of the second logical operation is logical false; and
obtaining an inverse of a seventh bit number and an inverse of a ninth bit number in the first bitstream correspondingly as a value assigned to a fifth bit and a value assigned to a seventh bit in the third bitstream and outputting the third bitstream with the assigned values as the fourth bitstream when the result of the second logical operation is logical true.

14. The decoding device according to claim 13 , wherein the step of processing the third bitstream to obtain the fourth bitstream based on the result of the second logical operation of the third specified bit and the fourth specified bit further comprises:
determining that the third specified bit and the fourth specified bit corresponds to a fifth bit and a sixth bit; and
exclusive-or-operating the fifth bit with the sixth bit to obtain the result of the second logical operation.

15. The decoding device according to claim 9 , wherein the first bitstream comprises ten bits.

16. The decoding device according to claim 15 , wherein a number of bits included in the fourth bitstream are the same as a number of bits included in the second bitstream and/or the third bitstream.

17. A non-transitory readable storage medium, wherein the non-transitory readable storage medium stores instructions, and the instructions, when executed, implements a decoding method as claimed in claim 1 .

18. The non-transitory readable storage medium according to claim 17 , wherein the step of obtaining the second bitstream based on the first bitstream comprises:
determining two flag bits in the first bitstream, wherein the two flag bits

Assignees

• Tcl China Star Optoelectronics Tech Co Ltd

Inventors

• Liu Jinfeng

Classifications

• H03M7/28

  Programmable structures, i.e. where the code converter contains apparatus which is operator-changeable to modify the conversion process · CPC title

• H04N19/42

  characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation (H04N19/635 takes precedence) · CPC title

• H03M7/14 Primary

  Conversion to or from non-weighted codes · CPC title

• H03M7/02 Primary

  Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word · CPC title

• H04N19/44 Primary

  Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder · CPC title