Communication device, and electronic device comprising same

Patent metadata

Field	Value
Publication number	US-12143104-B2
Application number	US-202218050934-A
Country	US
Kind code	B2
Filing date	Oct 28, 2022
Priority date	Sep 14, 2018
Publication date	Nov 12, 2024
Grant date	Nov 12, 2024

Abstract

A communication device is disclosed. The disclosed communication device comprises: a transmission circuit for generating a transmission signal by using a first field effect transistor (FET) and a signal inputted from a first control circuit, and transmitting the transmission signal to a second control circuit; and a reception circuit for generating a reception signal by using a second field effect transistor (FET) and a signal received from the second control circuit, and outputting the reception signal to the first control circuit.

First claim

What is claimed is:

1. An electronic apparatus comprising:
a first processor;
a second processor;
a first transmission circuit configured to, based on a first signal being input from the first processor, transmit a first transmission signal; and
a first reception circuit configured to receive the first transmission signal and send a second signal to the second processor;
wherein the first transmission circuit comprises a first Field Effect Transistor (FET) and a first Low Pass Filter (LPF) circuit and configured to generate the first transmission signal using the first signal and the first FET and transmit the first transmission signal to the first reception circuit;
wherein the first reception circuit comprises a second FET and a second LPF circuit and configured to receive the first transmission signal, generate the second signal using the first transmission signal and the second FET and send the second signal to the second processor;
wherein the first transmission circuit and the first reception circuit are connected via a wire;
a gate of the first FET of the first transmission circuit is connected to a first driving power;
a drain of the first FET is connected to the first LPF circuit;
a source of the first FET is connected to the first processor;
a gate of the second FET of the first reception circuit is connected to a second driving power;
a drain of the second FET is connected to the second LPF circuit; and
a source of the second FET is connected to the second processor.

2. The electronic apparatus as claimed in claim 1 , wherein a voltage level used by each of the first processor and the second processor is different.

3. The electronic apparatus as claimed in claim 1 , wherein a voltage level used by each of the first processor and the second processor is substantially the same.

4. The electronic apparatus as claimed in claim 1 , wherein the first transmission circuit and the first reception circuit have a symmetrical configuration based on the wire.

5. The electronic apparatus as claimed in claim 1 , wherein the first LPF circuit comprises:
a first resistance with one end connected to the drain of the first FET and the other end connected to an output of the first transmission circuit; and
a first capacitor with one end connected to the drain of the first FET and the other end grounded, and
wherein the first LPF circuit filters high frequency components.

6. The electronic apparatus as claimed in claim 5 , wherein the second LPF circuit comprises:
a second resistance with one end connected to the drain of the second FET and the other end connected to an input of the first reception circuit; and
a second capacitor with one end connected to the drain of the second FET and the other end grounded, and
wherein the second LPF circuit filters high frequency components.

7. The electronic apparatus as claimed in claim 6 , wherein the output of the first transmission circuit, which is connected to the first resistance, is connected to the wire,
wherein the input of the first reception circuit, which is connected to the second resistance, is connected to the wire, and
wherein a first transmission signal output at the output of the first transmission circuit is input to the input of the second reception circuit through the wire.

8. The electronic apparatus as claimed in claim 1 , wherein the first transmission circuit further comprises:
a third resistance with one end connected to the first processor and the other end connected to the first driving power; and
a fourth resistance with one end connected to the drain of the first FET and the other end connected to a third driving power.

9. The electronic apparatus as claimed in claim 8 , wherein the first transmission circuit is configured to, based on a voltage level of the second processor being higher than a voltage level of the first processor, transmit the first transmission signal to the first reception circuit by level-shifting the first signal input from the first processor by applying a voltage of the third driving power to the drain of the first FET, a voltage level of the third driving power being higher than a voltage level of the first driving power.

10. The electronic apparatus as claimed in claim 1 , wherein the first reception circuit comprises:
a fifth resistance with one end connected to the second processor and the other end connected to the second driving power; and
a sixth resistance with one end connected to the drain of the second FET and the other end connected to a fourth driving power.

11. The electronic apparatus as claimed in claim 10 , wherein the first reception circuit is configured to, based on a voltage level of the second processor being lower than a voltage level of the first processor, transmit the second signal to the second processor by level-shifting the first transmission signal transmitted from the first transmission circuit by applying a voltage of the fourth driving power to the drain of the second FET, a voltage level of the fourth driving power being higher than a voltage level of the second driving power.

12. The electronic apparatus as claimed in claim 1 , wherein the first FET and the second FET are N-Channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET).

13. The electronic apparatus as claimed in claim 1 , further comprising:
a second transmission circuit configured to, based on a third signal being input from the second processor, transmit a second transmission signal; and
a second reception circuit configured to receive the second transmission signal and send a fourth signal to the first processor,
wherein the second transmission circuit comprises a third FET and configured to generate the second transmission signal using the third signal and the third FET and transmit the second transmission signal to the second reception circuit, and
wherein the second reception circuit comprises a fourth FET and configured to generate the fourth signal using the second transmission signal and the fourth FET and send the fourth signal to the first processor.

14. The electronic apparatus as claimed in claim 13 , wherein the second transmission circuit further comprises a third LPF circuit;
wherein the second reception circuit further comprises a fourth LPF circuit;
wherein the second transmission circuit and the second reception circuit are connected via a wire, and the second transmission circuit and the second reception circuit have a symmetric configuration based on the wire;
a gate of the third FET of the second transmission circuit is connected to a fifth driving power;
a drain of the third FET is connected to the third LPF circuit;
a source of the third FET is connected to the second processor;
a gate of the fourth FET of the second reception circuit is connected to a sixth driving power;
a drain of the fourth FET is connected to the fourth LPF circuit; and
a source of the fourth FET is connected to the first processor.

15. The electronic apparatus as claimed in claim 14 , wherein the third LPF circuit comprises:
a seventh resistance with one end connected to the drain of the third FET and the other end connected to an output of the second transmission circuit; and
a third capacitor with one end connected to the drain of the third FET and the other end grounded, and
wherein the third LPF circuit filters high frequency components.

16. The electronic apparatus as claimed in claim 14 , wherein the fourth LPF circuit comprises:
an eighth resistance with one end connected to the drain of the fourth FET and the other end connected to an input of t

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yu Odo
• Byeon Sunghoon
• Kim Hwasung
• Jo Suho
• Ha Jonghun

Classifications

• H03K19/0013

  in field effect transistor circuits · CPC title

• H03K19/018592

  with a bidirectional operation · CPC title

• H03K19/01806

  Interface arrangements · CPC title

• H03K19/018507 Primary

  Interface arrangements · CPC title

• H03K19/0185 Primary

  using field effect transistors only · CPC title