Display panel and display apparatus

Patent metadata

Field	Value
Publication number	US-12142197-B2
Application number	US-202118271674-A
Country	US
Kind code	B2
Filing date	Dec 30, 2021
Priority date	Dec 30, 2021
Publication date	Nov 12, 2024
Grant date	Nov 12, 2024

Abstract

Disclosed are a display panel and a display apparatus, wherein the display panel includes a plurality of first signal lines extending along a first direction and a plurality of pixel units arranged in an array in the first direction and a second direction; at least one pixel unit among the plurality of pixel units includes a component group and a drive chip configured to drive the component group to emit light; the component group includes K light emitting elements, and the drive chip includes K signal channel terminals, K is a positive integer greater than or equal to 2; for a pixel unit in a j-th row and an i-th column, cathodes of the K light emitting elements are electrically connected with an i-th first signal line, and an anode of an s-th light emitting element is electrically connected with an s-th signal channel terminal of the drive chip.

First claim

The invention claimed is:

1. A display panel comprising: a plurality of first signal lines extending along a first direction and a plurality of pixel units arranged in an array in the first direction and a second direction; wherein the plurality of first signal lines are arranged along the second direction, and the first direction and the second direction intersect; at least one pixel unit among the plurality of pixel units comprises a component group and a drive chip configured to drive the component group to emit light; the component group comprises K light emitting elements, and the drive chip comprises K signal channel terminals, wherein K is a positive integer greater than or equal to 2; for a pixel unit in a j-th row and an i-th column, cathodes of the K light emitting elements are electrically connected with an i-th first signal line, and anodes of the K light emitting elements are respectively electrically connected with the K signal channel terminals in the drive chip, 1<j<M, 1<i <N, and i and j are positive integers, wherein the drive chip comprises: a low dropout regulator assembly, a data decoder, a data buffer, a data processing center, a data converter, and a drive assembly, a data signal terminal and an addressing signal terminal; the low dropout regulator assembly is electrically connected with the addressing signal terminal, the data decoder, and the data processing center, respectively, and has a circuitry for converting a signal of the addressing signal terminal into a first voltage signal to supply power to the data decoder and the data processing center; the data decoder is electrically connected with the data signal terminal and the data buffer respectively, and has a circuitry for decoding a data signal provided by the data signal terminal to generate a first data signal and transmitting the first data signal to the data buffer; the data buffer has a circuitry for storing the first data signal in bits; the data processing center is electrically connected with the data buffer and the data converter respectively, and has a circuitry for obtaining the first data signal stored in the data buffer, performing logical conversion on the first data signal stored in the data buffer to generate a second data signal, and transmitting the second data signal to the data converter; the data converter is electrically connected with the drive assembly, and has a circuitry for performing digital-to-analog conversion on the second data signal to generate a digital-analog conversion signal, performing pulse width modulation on the second data signal to form a pulse width modulation signal, and transmitting the digital-analog conversion signal and the pulse width modulation signal to the drive assembly; the drive assembly is electrically connected with the component group, and has a circuitry for generating a pulse width control signal according to the pulse width modulation signal, generating a constant current control signal according to the digital-analog conversion signal, and providing an electrical signal to the component group according to the pulse width control signal and the constant current control signal.

2. The display panel according to claim 1 , wherein the drive chip further comprises: a fixed voltage signal terminal;
a fixed voltage signal terminal of a drive chip of the pixel unit in the j-th row and the i-th column is electrically connected with the i-th first signal line.

3. The display panel according to claim 1 , further comprising: a plurality of second signal lines extending along the first direction and a plurality of third signal lines extending along the first direction, the plurality of second signal lines are arranged along the second direction, the plurality of third signal lines are arranged along the second direction;
a data signal terminal of a drive chip of the pixel unit in the j-th row and the i-th column is electrically connected with an i-th second signal line, and an addressing signal terminal of the drive chip of the pixel unit in the j-th row and the i-th column is electrically connected with an i-th third signal line.

4. The display panel according to claim 3 , wherein the i-th first signal line and the i-th second signal line are respectively located on two sides of an i-th column of pixel units, and the i-th second signal line and the i-th third signal line are located on a same side of the i-th column of pixel units.

5. The display panel according to claim 4 , wherein a component group of the pixel unit in the j-th row and the i-th column is located on a side of the drive chip close to the i-th first signal line.

6. The display panel according to claim 1 , wherein the first signal line is configured to transmit a ground signal.

7. The display panel according to claim 3 , wherein K=3, and the K light emitting elements comprise: a red light emitting element, a green light emitting element, and a blue light emitting element;
the drive chip comprises a first signal channel terminal, a second signal channel terminal, and a third signal channel terminal;
the first signal channel terminal is electrically connected with an anode of the red light emitting element;
the second signal channel terminal is electrically connected with an anode of the green light emitting element;
the third signal channel terminal is electrically connected with an anode of the blue light emitting element.

8. A display apparatus, comprising: the display panel according to claim 1 .

9. The display panel according to claim 1 , further comprising: a first Direct Current (DC) converter;
the first DC converter is electrically connected with a third signal line and has a circuitry for transmitting a signal to the third signal line.

10. The display panel according to claim 9 , wherein the low dropout regulator assembly further has a circuitry for converting the signal of the addressing signal terminal into a second voltage signal.

11. The display panel according to claim 10 , wherein the low dropout regulator assembly comprises: a first low dropout regulator and a second low dropout regulator;
the first low dropout regulator is electrically connected with the addressing signal terminal, the data decoder, and the data processing center, respectively, and has a circuitry for converting the signal of the addressing signal terminal into the first voltage signal to supply power to the data decoder and the data processing center;
the second low dropout regulator is electrically connected with the addressing signal terminal and has a circuitry for converting the signal of the addressing signal terminal into the second voltage signal.

12. The display panel according to claim 11 , wherein the low dropout regulator assembly further has a circuitry for converting the signal of the addressing signal terminal into a third voltage signal;
the drive assembly has a circuitry for providing an electrical signal to the component group according to the pulse width control signal, the constant current control signal, the second voltage signal, and the third voltage signal.

13. The display panel according to claim 12 , wherein the low dropout regulator assembly further comprises: a third low dropout regulator;
the third low dropout regulator is connected with the addressing signal terminal and has a circuitry for converting the signal of the addressing signal terminal into the third voltage signal.

14. The display panel according to claim 13 , wherein the drive assembly comprises: a first driver, a second driver, and a third driver; the first driver is electrically connected with the data converter, the second low dropout regulator, and a first signal ch

Assignees

• Boe Mled Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Gu Qibing
• Hu Guofeng
• Li Xiuling
• Fu Bao
• Li Jiayi
• Wang Xiurong
• Lin Yicheng
• Shi Lingyun

Classifications

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2320/0626

  for control of overall brightness · CPC title

• G09G2320/041

  Temperature compensation · CPC title

• G09G2310/0291

  Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title

• G09G2300/0828

  forming a digital to analog [D/A] conversion circuit · CPC title