Single photon avalanche detector, method for use therefore and method for its manufacture

Patent metadata

Field	Value
Publication number	US-12140707-B2
Application number	US-201917274914-A
Country	US
Kind code	B2
Filing date	Sep 9, 2019
Priority date	Sep 10, 2018
Publication date	Nov 12, 2024
Grant date	Nov 12, 2024

Abstract

A single photon avalanche diode (SPAD) device is presented. The SPAD device comprising: a Si-based avalanche layer formed over an n-type semiconductor contact layer; a p-type charge sheet layer formed in or on the avalanche layer, the p-type charge sheet layer having an in-plane width; a Ge-based absorber layer, formed over the charge sheet layer and/or the avalanche layer, and overlapping the charge sheet layer, the Ge-based absorber layer having an in-plane width; wherein, at least in one in-plane direction, the in-plane width of the Ge-based absorber layer is greater than the in-plane width of the p-type charge sheet layer.

First claim

The invention claimed is:

1. A single photon avalanche diode (SPAD) device comprising:
a Si-based avalanche layer formed over an n-type semiconductor contact layer;
a p-type charge sheet layer formed in or on the avalanche layer, the p-type charge sheet layer having an in-plane width;
a Ge-based absorber layer, formed over the charge sheet layer and/or the avalanche layer, and overlapping the charge sheet layer, the Ge-based absorber layer having an in-plane width;
wherein, at least in one in-plane direction, the in-plane width of the Ge-based absorber layer is greater than the in-plane width of the p-type charge sheet layer.

2. A SPAD device according to claim 1 wherein in all in-plane directions, the in-plane width of the Ge-based absorber layer is greater than the in-plane width of the p-type charge sheet layer.

3. A SPAD device according to claim 1 , further comprising:
a p-type semiconductor contact layer formed over the absorber layer, the p-type semiconductor contact layer having an in-plane width,
wherein at least part of the p-type semiconductor contact layer is formed substantially in register with at least part of the p-type charge sheet layer, with the Ge-based absorber layer interposed between them.

4. A SPAD device according to claim 3 wherein, at least in one in-plane direction, the in-plane width of the Ge-based absorber layer is greater than the in-plane width of the p-type semiconductor contact layer.

5. A SPAD device according to claim 3 wherein, in all in-plane directions, the in-plane width of the Ge-based absorber layer is greater than the in-plane width of the p-type semiconductor contact layer.

6. A SPAD device according to claim 3 wherein, in all in-plane directions, the in-plane width of the Ge-based absorber layer is greater than the in-plane width of the p-type semiconductor contact layer and greater than the in-plane width of the p-type charge sheet layer.

7. A SPAD device according to claim 3 wherein the entire p-type semiconductor contact layer is formed substantially in register with at least part of the p-type charge sheet layer.

8. A SPAD device according to claim 3
wherein at least in one in-plane direction, the in-plane width of the p-type charge sheet layer is greater than the in-plane width of the p-type semiconductor contact layer, and
wherein the Ge-based absorber layer has a sidewall in said in-plane direction and the charge sheet layer has a lateral edge in said in-plane direction, and either:

(a) when the Ge-based absorber layer has a thickness of at least 1 μm, the distance in the in-plane direction between the lateral edge of the charge sheet layer and the sidewall of the Ge-based absorber layer is at least 1 μm greater than the thickness of the Ge-based absorber layer; or
(b) when the Ge-based absorber layer has a thickness of less than 1 μm, the distance in the in-plane direction between the lateral edge of the charge sheet layer and the sidewall of the Ge-based absorber layer is at least 1.0 μm.

9. A SPAD device according to claim 8 wherein the distance in the in-plane direction between the lateral edge of the charge sheet layer and the sidewall of the Ge-based absorber layer is at least 5 μm.

10. A SPAD device according to claim 3 , wherein the p-type semiconductor contact layer has a lateral edge in said in-plane direction and the charge sheet layer has a lateral edge in said in-plane direction, and either:
(c) when the width of the charge sheet is at least 25 μm, a distance in the in-plane direction between the lateral edge of the charge sheet layer and the lateral edge of the p-type semiconductor contact layer is at least 2 μm; or
(d) when the width of the charge sheet is less than 25 μm, a distance in the in-plane direction between the lateral edge of the charge sheet layer and the lateral edge of the p-type semiconductor contact layer is at least 1 μm.

11. A SPAD device according to claim 1 wherein the charge sheet layer has a maximum doping concentration at a depth in the range 10-100 nm from the surface of the Si-based avalanche layer.

12. A SPAD array comprising at least a 1×2 arrangement of SPAD devices each according to claim 1 and formed on a common substrate.

13. A SPAD array according to claim 12 wherein the respective Ge-based absorber layers of adjacent SPAD devices are laterally isolated by:
(i) etching of a continuous Ge-based absorber layer to at least the depth of the p-type charge sheet layer in order to form the respective Ge-based absorber layers of adjacent SPAD devices; or
(ii) doping of a continuous Ge-based absorber layer to at least the depth of the p-type charge sheet layer in order to form the respective Ge-based absorber layers of adjacent SPAD devices; or
(iii) selective area growth of the respective Ge-based absorber layers within patterned electrically insulating layers in order to form the respective Ge absorber layers of adjacent SPAD devices.

14. A LIDAR system comprising a source of light of wavelength in the range 0.9-2.0 μm and a SPAD device according to claim 1 .

15. Use of a SPAD device according to claim 1 in the detection of at least one photon with wavelength in the range 0.9-2.0 μm.

16. A method of manufacture of a SPAD device according to claim 1 wherein the p-type charge sheet layer is formed by selective area implantation into the Si-based avalanche layer.

17. A method according to claim 16 wherein the charge sheet layer is activated by annealing at a temperature of at least 850° C., before deposition of the Ge-based absorber layer.

18. A method according to claim 16 wherein at least one upper and/or side surface of the Ge-based absorber layer is passivated.

19. A method according to claim 18 wherein the passivation is provided by a GeO 2 layer thermally grown and protected by an Al 2 O 3 layer.

20. A single photon avalanche diode (SPAD) device comprising:
a Si-based avalanche layer on an n-type semiconductor contact layer;
a p-type charge sheet layer in or on the avalanche layer, the p-type charge sheet layer having an in-plane width;
a Ge-based absorber layer, over the charge sheet layer and/or the avalanche layer, and overlapping the charge sheet layer, the Ge-based absorber layer having an in-plane width; and
a p-type semiconductor contact layer over the Ge-based absorber layer, the p-type semiconductor contact layer having an in-plane width,
wherein, at least in one in-plane direction, the in-plane width of the Ge-based absorber layer is greater than the in-plane width of the p-type charge sheet layer, and
wherein, in all in-plane directions, the in-plane width of the Ge-based absorber layer is greater than the in-plane width of the p-type semiconductor contact layer.

Assignees

• Univ Glasgow Court
• Univ Heriot Watt

Inventors

• Paul Douglas John
• Dumas Derek
• Kirdoda Jaroslaw
• Millar Ross W
• Mirza Muhammad M
• Buller Gerald S
• Vines Peter
• Kuzmenko Kateryna

Classifications

• H10F30/2255 Primary

  in which the active layers form heterostructures, e.g. SAM structures · CPC title

• H10F71/00

  Manufacture or treatment of devices covered by this subclass (patterning processes to connect thin photovoltaic cells in integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/33; manufacture or treatment of encapsulations or containers for integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/80; manufacture or treatment of integrated devices, or assemblies of multiple devices, comprising at least one element in which radiation controls the flow of current H10F39/00) · CPC title

• G01J1/44

  Electric circuits {(for command of an exposure part G03B7/02)} · CPC title

• G01S7/4912

  Receivers · CPC title

• G01S7/4863 Primary

  Detector arrays, e.g. charge-transfer gates · CPC title