Low latency post-quantum signature verification for fast secure-boot

Patent metadata

Field	Value
Publication number	US-12137169-B2
Application number	US-202217854911-A
Country	US
Kind code	B2
Filing date	Jun 30, 2022
Priority date	Jun 28, 2019
Publication date	Nov 5, 2024
Grant date	Nov 5, 2024

Abstract

In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described.

First claim

What is claimed is:

1. An apparatus comprising:
host processor circuitry; and
a hardware accelerator, coupled to the host processor circuitry, including a SHAKE hardware accelerator, the hardware accelerator comprising:
memory to store a set of Extended Merkle Signature Scheme (XMSS) inputs associated with multiple XMSS operations,
XMSS verification circuitry to manage multiple XMSS verification functions associated with the multiple XMSS operations, wherein
a first XMSS verification function is a public key generation to be performed by an execution of a chain function that is to use the SHAKE hardware accelerator to generate public key components,
a second XMSS verification function is L-tree computation that is to combine the public key components by using the SHAKE hardware accelerator,
a third XMSS verification function is a tree-hash computation that is to use an output of the L-tree computation and the SHAKE hardware accelerator to generate a root node, wherein the SHAKE hardware accelerator comprises a 1600-bit state register used to receive the set of XMSS inputs including one or more of a first set of inputs for each chain function, a second set of inputs for hashes involved in an L-Tree computation, a third set of inputs for a Merkle tree root node computation, or a 256-bit message input.

2. The apparatus of claim 1 , wherein the hardware accelerator is further to:
assert a busy signal on a communication bus; and
switch to a protected mode in which external read/write operations are disregarded.

3. The apparatus of claim 1 , wherein the SHAKE hardware accelerator is to support a SHAKE-128 operation or a SHAKE-256 operation.

4. The apparatus of claim 1 , wherein the processor circuitry to facilitate the SHAKE hardware accelerator to:
perform a first set of 24 SHA3 rounds using the first set of inputs or no inputs; and
generate a first 128-bit output or a first 256-bit output.

5. A method comprising:
receiving a set of Extended Merkle Signature Scheme (XMSS) inputs associated with multiple XMSS operations, wherein a hardware accelerator includes a SHAKE hardware accelerator, wherein the set of XMSS inputs is used by an XMSS verification manager circuitry to manage multiple XMSS verification functions associated with the multiple XMSS operations; and
performing the multiple XMSS operations to:
generate public key components using chain function that is to use the SHAKE hardware accelerator,
perform an L-tree computation that is to combine the public key components using the SHAKE hardware accelerator,
perform a tree-hash computation using an output of the L-tree computation and the SHAKE hardware accelerator to generate a root node, wherein the SHAKE hardware accelerator comprises a 1600-bit state register used to receive the set of XMSS inputs including one or more of a first set of inputs for each chain function, a second set of inputs for hashes involved in an L-Tree computation, a third set of inputs for a Merkle tree root node computation, or a 256-bit message input.

6. The method of claim 5 , further comprising:
asserting a busy signal on a communication bus; and
switching to a protected mode in which external read/write operations are disregarded.

7. The method of claim 5 , wherein the SHAKE hardware accelerator supports a SHAKE-128 operation or a SHAKE-256 operation.

8. The method of claim 5 , further comprising:
performing a first set of 24 SHA3 rounds using the first set of inputs or no inputs; and
generating a first 128-bit output or a first 256-bit output.

9. A non-transitory computer-readable medium having stored thereon instructions which, when executed, cause a computing device to perform operations comprising:
receiving a set of Extended Merkle Signature Scheme (XMSS) inputs associated with multiple XMSS operations, wherein a hardware accelerator includes a SHAKE hardware accelerator, wherein the set of XMSS inputs is used by an XMSS verification manager circuitry to manage multiple XMSS verification functions associated with the multiple XMSS operations; and
performing the multiple XMSS operations to:
generate public key components using chain function that is to use the SHAKE hardware accelerator,
perform an L-tree computation that is to combine the public key components using the SHAKE hardware accelerator,
perform a tree-hash computation using an output of the L-tree computation and the SHAKE hardware accelerator to generate a root node, wherein the SHAKE hardware accelerator comprises a 1600-bit state register used to receive the set of XMSS inputs including one or more of a first set of inputs for each chain function, a second set of inputs for hashes involved in an L-Tree computation, a third set of inputs for a Merkle tree root node computation, or a 256-bit message input.

10. The computer-readable medium of claim 9 , wherein the operations further comprise:
asserting a busy signal on a communication bus; and
switching to a protected mode in which external read/write operations are disregarded.

11. The computer-readable medium of claim 9 , wherein the operations further comprise:
applying a one-time signature function process to the set of XMSS inputs; and
invoking a chain function processor to apply a chain function to facilitate the one-time signature function.

12. The computer-readable medium of claim 9 , wherein the SHAKE hardware accelerator supports a SHAKE-128 operation or a SHAKE-256 operation.

13. The computer-readable medium of claim 9 , wherein the operations further comprise:
performing a first set of 24 SHA3 rounds using the first set of inputs or no inputs; and
generating a first 128-bit output or a first 256-bit output.

Assignees

• Intel Corp

Inventors

• Ghosh Santosh
• Suresh Vikram
• Mathew Sanu
• Sastry Manoj
• Reinders Andrew H
• Kumar Raghavan
• Misoczki Rafael

Classifications

• H04L9/50

  using hash chains, e.g. blockchains or hash trees · CPC title

• H04L9/30

  Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy · CPC title

• H04L9/0877

  using additional device, e.g. trusted platform module [TPM], smartcard, USB or hardware security module [HSM] · CPC title

• H04L9/0643

  Hash functions, e.g. MD5, SHA, HMAC or f9 MAC · CPC title

• H04L9/0852 Primary

  Quantum cryptography (transmission systems employing electromagnetic waves other than radio waves, e.g. light, infrared H04B10/00; wavelength-division multiplex systems H04J14/02; WDM arrangements H04J14/03) · CPC title